LC72131K/KMA Datasheet by ON Semiconductor

ON Semiconductor”

July 2017 - Rev. 1 LC72131K_KMA/D

www.onsemi.com

ORDERING INFORMATION

See detailed ordering and shipping information on page 23 of this data sheet.

* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and

the bus addresses are controlled by ON Semiconductor.

LC72131K, LC72131KMA

PLL Frequency Synthesizer for

Tuners in Radio/Cassette Players

Overview

The LC72131K and LC72131KMA are PLL frequency synthesizers for

use in tuners in radio/cassette players.

They allow high-performance AM/FM tuners to be implemented easily.

Features

 High speed programmable dividers

 FMIN: 10 to 160 MHz ····· pulse swallower

(built-in divide-by-two prescaler)

 AMIN: 2 to 40 MHz ······ pulse swallower

0.5 to 10 MHz ····· direct division

 IF counter

 IFIN: 0.4 to 12 MHz ······ AM/FM IF counter

 Reference frequencies

 Twelve selectable frequencies (4.5 or 7.2 MHz crystal)

 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1 kHz

 Phase comparator

 Dead zone control

 Unlock detection circuit

 Deadlock clear circuit

 Built-in MOS transistor for forming an active low-pass filter

 I/O ports

 Dedicated output ports: 4

 Input or output ports: 2

 Support clock time base output

 Serial data I/O

 Support CCB* format communication with the system controller.

 Operating ranges

 Supply voltage : 4.5 to 5.5 V

 Operating temperature : 40 to +85C

 Packages

 LC72131K : DIP22S (300mil)

 LC72131KMA : MFP20J (300mil)

PDIP22 / DIP22S (300 mil)

[LC72131K]

SOIC20W / MFP20J (300 mil)

[LC72131KMA]

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Specifications

Absolute Maximum Ratings at Ta = 25C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings Unit

Supply voltage VDD max VDD 0.3 to +7.0 V

Maximum input voltage VIN1 max CE, CL, DI, AIN 0.3 to +7.0 V

VIN2 max XIN, FMIN, AMIN, IFIN 0.3 to VDD+0.3 V

VIN3 max IO1, IO2 0.3 to +15 V

Maximum output

voltage

VO1 max DO 0.3 to +7.0 V

VO2 max XOUT, PD 0.3 to VDD+0.3 V

VO3 max BO1 to BO4, IO1, IO2,

AOUT

0.3 to +15 V

Maximum output

current

IO1 max BO1 0 to 3.0 mA

IO2 max DO, AOUT 0 to 6.0 mA

IO3 max BO2 to BO4, IO1, IO2 0 to 10 mA

Allowable power

dissipation

Pd max Ta  85C

[LC72131K] 350 mW

Ta  85C

[LC72131KMA] 180 mW

Operating temperature Topr 40 to +85 C

Storage temperature Tstg 55 to +125 C

Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when

using the IC.

Allowable Operating Ranges at Ta = 40C to +85C, VSS = 0 V

Parameter Symbol Pins Conditions Ratings unit

min typ max

Supply voltage VDD V

DD 4.5 5.5 V

Input high-level voltage VIH1 CE, CL, DI 0.7VDD 6.5 V

VIH2 IO1, IO2 0.7VDD 13 V

Input low-level voltage VIL CE, CL, DI, IO1, IO2 0

0.3VDD V

Output voltage VO1 DO 0 6.5 V

VO2 BO1 to BO4, IO1, IO2,

AOUT

0 13 V

Input frequency fIN1 XIN VIN1 1.0 8.0 MHz

fIN2 FMIN VIN2 10 160 MHz

fIN3 AMIN VIN3 2.0 40 MHz

fIN4 AMIN VIN4 0.5 10 MHz

fIN5 IFIN VIN5 0.4 12 MHz

Supported crystals X'tal XIN, XOUT Note 1 4.0 8.0 MHz

Input amplitude

High-level clock pulse

width tφH CL [Figure 1]

[Figure 2] 160 ns

Low-level clock pulse

width

VIN1 XIN fIN1 400 1500 mVrms

VIN2-1 FMIN f = 10 to 130 MHz 40 1500 mVrms

VIN2-2 FMIN f = 130 to 160 MHz 70 1500 mVrms

VIN3 AMIN fIN3 40 1500 mVrms

VIN4 AMIN fIN4 40 1500 mVrms

VIN5 IFIN fIN5 (IFS=1) 40 1500 mVrms

VIN6 IFIN fIN5 (IFS=0) 70 1500 mVrms

Data setup time tSU DI, CL Note 2 0.75

s

Data hold time tHD DI, CL Note 2 0.75

s

Clock low-level time tCL CL Note 2 0.75

s

Clock high-level time tCH CL Note 2 0.75

s

CE wait time tEL CE, CL Note 2 0.75

s

CE setup time tES CE, CL Note 2 0.75

s

CE hold time tEH CE, CL Note 2 0.75

s

Data latch change time tLC Note 2 0.75

s

Data output time tDC DO, CL Differs depending

on the value of the

pull-up resistor.

Note 2

0.35

s

tDH DO, CE

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,

damage may occur and reliability may be affected.

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Note 1: Recommended crystal oscillator CI values:

CI  120 Ω (For a 4.5 MHz crystal)

CI  70 Ω (For a 7.2 MHz crystal)

The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other

factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability.

Note 2: Refer to "Serial Data Timing".

Electrical Characteristics in the Allowable Operating Ranges

Parameter Symbol Pins Conditions Ratings unit

min typ max

Built-in feedback

resistance

Rf1 XIN 1.0 MΩ

Rf2 FMIN 500 kΩ

Rf3 AMIN 500 kΩ

Rf4 IFIN 250 kΩ

Built-in pull-down

resistor

Rpd1 FMIN 200 kΩ

Rpd2 AMIN 200 kΩ

Hysteresis VHYS

CE, CL, DI, IO1, IO2 0.1VDD V

Output high-level

voltage

VOH PD IO = 1 mA VDD0.1 V

Output low-level

voltage

VOL1 PD IO = 1 mA 1.0 V

VOL2 BO1 IO = 0.5 mA 0.5 V

IO = 1 mA 1.0 V

VOL3 DO IO = 1 mA 0.2 V

IO = 5 mA 1.0 V

VOL4 BO2 to BO4, IO1, IO2 IO = 1 mA 0.2 V

IO = 5 mA 1.0 V

IO = 8 mA 1.6 V

VOL5 AOUT

IO = 1 mA

AIN = 1.3 V

0.5 V

Input high-level

current

IIH1 CE, CL, DI VI = 6.5 V 5.0

A

IIH2 IO1, IO2 VI = 13 V 5.0

A

IIH3 XIN VI = VDD 2.0 11

A

IIH4 FMIN, AMIN VI = VDD 4.0 22

A

IIH5 IFIN VI = VDD 8.0 44

A

IIH6 AIN VI = 6.5 V 200 nA

Input low-level current IIL1 CE, CL, DI VI = 0 V 5.0

A

IIL2 IO1, IO2 VI = 0 V 5.0

A

IIL3 XIN VI = 0 V 2.0 11

A

IIL4 FMIN, AMIN VI = 0 V 4.0 22

A

IIL5 IFIN VI = 0 V 8.0 44

A

IIL6 AIN VI = 0 V 200 nA

Output off leakage

current

IOFF1 BO1 to BO4, AOUT,

IO1, IO2

VO = 13 V

5.0

A

IOFF2 DO VO = 6.5 V 5.0

A

High-level three-state

off leakage current

IOFFH PD VO = VDD 0.01 200 nA

Low-level three-state

off leakage current

IOFFL PD VO = 0 V 0.01 200 nA

Input capacitance CIN FMIN 6 pF

Current drain IDD1 VDD X'tal = 7.2 MHz

fIN2 = 130 MHz

VIN2 = 40 mVrms

5 10 mA

IDD2 VDD PLL block stopped

(PLL INHIBIT)

X'tal oscillator

operating

(X'tal = 7.2 MHz)

0.5 mA

IDD3 VDD PLL block stopped

X'tal oscillator

operating

10

A

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended

Operating Ranges limits may affect device reliability.

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be

indicated by the Electrical Characteristics if operated under different conditions.

ISU ‘HD H W % % 9 IH IH IEH ISU ‘HD >

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4

Serial Data Timing

tCL

tEH

tES

tHD tSU

Old New

tLC

tDH tDC

tEL

tCH

When stopped with CL high

VIL

VIH V

IH

VIH

VIH VIH

VIH

VIL VIL

VIL

DO

Internal

data latch

CL

DI

CE



 



 



  



tCL

tEH tES

tHD tSU

Old New

tLC

tDH tDC tDC

tEL

tCH



When stopped with CL low

VIL

VIL VIH VIH

VIH

VIH VIH

VIH

VIL

DO

Internal

data latch

CL

DI

CE



 



  



  



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Package Dimensions

unit : mm

[LC72131K]

PDIP22 / DIP22S (300 mil)

CASE 646AV

ISSUE A

XXXXXXXXXX

YMDDD

GENERIC

MARKING DIAGRAM*

*This information is generic.

XXXXX = Specific Device Code

Y = Year

M = Month

DDD = Additional Traceability Data

to

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Package Dimensions

unit : mm

[LC72131KMA]

SOIC20W / MFP20J (300 mil)

CASE 751DE

ISSUE O

to

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Pin Assignments

Block Diagram

IO2

12 13 14 15 16 17 18 19 20 21

22

1 2 3 4 5 6 7 8 9 10 11

XOUT

IFIN

NC

AMIN

FMIN

VDD

PD

AIN

AOUT

VSS

CE

NC

XIN

DO

CL

DI

BO3

BO2

BO1

IO1

BO4

LC72131K

Top view

PD

IFIN

AMIN

CE

DI

CL

DO

VSS

VDD

FMIN

XOUT

XIN

UNIVERSAL

COUNTER

UNLOCK

DETECTOR

PHASE DETECTOR

CHARGE PUMP

REFERENCE

DIVIDER

DATA SHIFT REGISTER

LATCH

12bits PROGRAMMABLE

DIVIDER

SWALLOW COUNTER

1/16,1/17 4bits

POWER

ON

RESET

CCB

I/F

1/2

AIN

AOUT

BO1 BO2 BO3 BO4 IO1 IO2

IO2

11 12 13 14 15 16 17 18 19

20

1 2 3 4 5 6 7 8 9 10

XOUT

IFIN

AMIN

FMIN

VDD

PD

AIN

AOUT

VSS CE

XIN

DO

CL

DI

BO3

BO2

BO1

IO1

BO4

LC72131KMA

Top view

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8

Pin Functions

Symbol

Pin No.

Type Functions Circuit configuration

LC72131K LC72131KMA

XIN

XOUT

1

22

1

20

X'tal OSC Crystal resonator connection

(4.5MHz/7.2MHz)

FMIN 16 14 Local

oscillator

signal input

FMIN is selected when the serial data input DVS bit is set to 1.

The input frequency range is from 10 to 160MHz.

The input signal passes through the internal divide-by-two

prescaler and is input to the swallow counter.

The divisor can be in the range 272 to 65535. However,

since the signal has passed through the divide-by-two

prescaler, the actual divisor is twice the set value.

AMIN 15 13 Local

oscillator

signal input

AMIN is selected when the serial data input DVS bit is set to 0.

When the serial data input SNS bit is set to 1:

 The input frequency range is 2 to 40MHz.

 The signal is directly input to the swallow counter.

 The divisor can be in the range 272 to 65535, and the divisor

used will be the value set.

When the serial data input SNS bit is set to 0:

 The input frequency range is 0.5 to 10MHz.

 The signal is directly input to a 12-bit programmable divider.

 The divisor can be in the range 4 to 4095, and the divisor

used will be the value set.

CE 3 2 Chip enable Set this pin high when inputting (DI) or outputting (DO) serial

data.

DI 4 3 Input data Inputs serial data transferred from the controller to the

LC72131K/KMA.

CL 5 4 Clock Used as the synchronization clock when inputting (DI) or

outputting (DO) serial data.

DO 6 5 Output data Outputs serial data transferred from the LC72131K/KMA to the

controller.

The content of the output data is determined by the serial data

DOC0 to DOC2.

VDD 17 15 Power supply The LC72131K/KMA power supply pin (VDD=4.5 to 5.5V)

The power on reset circuit operates when power is first applied. -

VSS 21 19 Ground The LC72131K/KMA ground -

BO1

BO2

BO3

BO4

7

8

9

10

6

7

8

9

Output port Dedicated output pins

The output states are determined by BO1 to BO4 bits in

the serial data.

Data: 0=open, 1=low

A time base signal (8Hz) can be output from the BO1 pin.

(When the serial data TBC bit is set to 1.)

Care is required when using the BO1 pin, since it has a higher on

impedance that the other output ports (pins BO2 to BO4).

IO1

IO2

11

13

10

12

I/O port I/O dual-use pins

The direction (input or output) is determined by bits IOC1 and

IOC2 in the serial data.

Data: 0=input port, 1=output port

When specified for use as input ports:

The state of the input pin is transmitted to the controller over

the DO pin.

Input state: low=0 data value

high=1 data value

When specified for use as output ports:

The output states are determined by the IO1 and IO2 bits in

the serial data.

Data: 0=open, 1=low

These pins function as input pins following a power on reset.

Continued on next page.

S

IeveT \S empm lmm the PD pm Swmﬂarly‘ when tha| Irequency \S Teweh 3 \0w TeveT \S umput The PD pm gees u; The mgh \mpedanbe share when The (requehmes ma|ch AIN 19 17 LPF amphher The ﬁrchanne‘ MOS (ranswsmr used Tar the PLL achve AouT 20 18 (ranswsmrs \qupass Mar IFWN 12 11 IF eeumer Accepts eh mpm m the lrequency range m 4 m 12MHZ The mpm swgnal .s aheeuy hehsmlued m The \F wumer The resuﬂ ‘5 umpm sramhg The MSB m The IF counter uslng The DO pln Four measuremem penads are suppoﬂed 4‘ a. 32‘ and 54m: TW “ DI Control Data (Serial Data Input) Structure In INl mode |2| 1N2 mode *—v—’\—v—“—H\—v—”—v—“—v—“—v—“—HLHLY4‘W—’ www.0nsemi.com 9

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9

Continued from preceding page.

Symbol

Pin No.

Type Functions Circuit configuration

LC72131K LC72131KMA

PD 18 16 Charge pump

output

PLL charge pump output

When the frequency generated by dividing the local oscillator

frequency by N is higher than the reference frequency, a high

level is output from the PD pin.

Similarly, when that frequency is lower, a low level is output.

The PD pin goes to the high impedance state when the

frequencies match.

AIN

AOUT

19

20

17

18

LPF amplifier

transistors

The n-channel MOS transistor used for the PLL active

low-pass filter.

IFIN 12 11 IF counter Accepts an input in the frequency range 0.4 to 12MHz.

The input signal is directly transmitted to the IF counter.

The result is output starting the MSB of the IF counter using the

DO pin.

Four measurement periods are supported: 4, 8, 32, and 64ms.

DI Control Data (Serial Data Input) Structure

[1] IN1 mode

[2] IN2 mode

R2

R1

R0

(3) IF-CTR

XS

CTE

DVS

SNS

P15

P14

P13

P12

P11

P10

(1) P-CTR

(2) R-CTR

P9

P8

P7

P6

P5

P4

P3

P2

P1

P0

R3

address

0 0 1 0 1 0 0

DI 0

First Data IN1

TEST1

TEST0

IFS

(12) TEST

(11) IFS

(10) PD-C

(5) O-PORT

(13) Don’t care

(6) DO-C

(9) TIME

DLC

TBC

GT1

GT0

DZ1

DZ0

UL1

UL0

DOC2

DOC1

(7) UNLOCK

(4) IO-C

(8) DZ-C

(3) IF-CTR

DOC0

DNC

BO4

BO3

BO2

BO1

IO2

IO1

IOC2

IOC1

TEST2

address

0 0 1 0 1 0 0

DI 1

First Data IN2

DVS‘ st Reverence mwuer da|a R0 «0 R3 x5 \F coumer control da|a CTE GTO GT1

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10

Control Data Functions

No. Control block/data Functions Related data

(1) Programmable

divider data

P0 to P15

DVS, SNS

Data that sets the divisor of the programmable divider.

A binary value in which P15 is the MSB. The LSB changes depending on

DVS and SNS. (*: don’t care)

Note: P0 to P3 are ignored when P4 is the LSB.

Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches

the input frequency range. (*: don’t care)

Note: See the “Programmable Divider Structure” item for more information.

(2) Reference divider

data

R0 to R3

XS

Reference frequency (fref) selection data.

Note *: PLL INHIBIT

The programmable divider block and the IF counter block are stopped, the FMIN, AMIN,

and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the

high impedance state.

Crystal resonator selection

XS=0: 4.5MHz

XS=1: 7.2MHz

The 7.2MHz frequency is selected after the power-on reset.

(3) IF counter control

data

CTE

GT0, GT1

IF counter measurement start data

CTE=1: Counter start

=0: Counter reset

Determines the IF counter measurement period.

Note: See the “IF Counter Structure” item for more information.

IFS

Continued on next page.

Twice the value of the setting

The value of the setting

272 to 65535

4 to 4095

Actual divisor Divisor setting (N) LSB SNS

P0

P4

*

1

0

1

0

DVS

10 to 160MHz

2 to 40MHz

0.5 to 10MHz

FMIN

AMIN

Input frequency range Input pin SNS

*

1

0

1

0

DVS

1 * PLL INHIBIT

* PLL INHIBIT + X'tal OSC STOP

1

0 1

1 1

0

1

0

1

3

15

10

9

5

1

0

1

0

1

0

1

0

1

100kHz

50

25

12.5

6.25

3.125

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Reference frequency R0 R1 R2 R3

Wait time (ms) Measurement time (ms) GT0 GT1

3 to 4

7 to 8

4

8

32

64

0

1

0

1

0

1

(7) Unlock delecuun da|a ULO. uu

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11

Continued from preceding page.

No. Control block/data Functions Related data

(4) I/O port specification

data

IOC1, IOC2

Specifies the I/O direction for the bidirectional pins IO1 and IO2.

Data: 0=input mode, 1=output mode

(5) Output port data

BO1 to BO4

IO1, IO2

Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports

Data: 0=open, 1=low

The data=0 (open) state is selected after the power-on reset.

IOC1

IOC2

(6) DO pin control data

DOC0

DOC1

DOC2

Data that determines the DO pin output

The open state is selected after the power-on reset.

Note: 1. end-UC: Check for IF counter measurement completion

(1) When end-UC is set and the IF counter is started (i.e., when CTE is changed from

zero to one), the DO pin automatically goes to the open state.

(2) When the IF counter measurement completes, the DO pin goes low to indicate the

measurement completion state.

(3) Depending on serial data I/O (CE: high) the DO pin goes to the open state.

Note: 2. Goes to the open state if the I/O pin is specified to be an output port.

Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE

high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).

Also, the DO pin during a data output period (an OUT mode period with CE high) will

output the contents of the internal DO serial data in synchronization with the CL pin

signal, regardless of the state of the DO control data (DOC0 to DOC2).

UL0, UL1

CTE

IOC1

IOC2

(7) Unlock detection

data

UL0, UL1

Selects the phase error (E) detection width for checking PLL lock.

A phase error in excess of the specified detection width is seen as an unlocked state.

Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero.

DOC0

DOC1

DOC2

Continued on next page.

Open

The IO1 pin state *2

The IO2 pin state *2

Open

Low when the unlock state is detected

end-UC *1

Open

Do pin state DOC0 DOC1

0

1

0

1

0

1

0

1

0

1

0

1

0

DOC2



(1) Count start (3)CE: High (2) Count end

DO pin



Open

E is output directry

E is extended by 1 to 2ms



stopped

0

0.55s

1.11

Detector output E detection width UL0

0

1

0

1

0

1

UL1

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12

Continued from preceding page.

No. Control block/data Functions Related data

(8) Phase comparator

control data

DZ0, DZ1

• Controls the phase comparator dead zone.

Dead zone width: DZA<DZB<DZC<DZD

(9) Clock time base

TBC

Setting TBC to one causes an 8Hz, 40% duty clock time base signal to be output from the BO1

pin. (BO1 data is invalid in this mode.)

BO1

(10) Charge pump control

data

DLC

Forcibly controls the charge pump output.

Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO

oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and

setting Vtune to VCC. (This is the deadlock clearing circuit.)

(11) IF counter control

data

IFS

This data must be set 1 in normal mode.

IFS Though if this value is set to zero, the system enters input sensitivity degradation mode,

and the sensitivity is reduced to 10 to 30mVrms.

* See the “IF Counter Operation” item for details.

(12) LSI test data

TEST0 to 2

LSI test data

TEST0

TEST1 These values must all be set to 0.

TEST2

These test data are set to 0 automatically after the power-on reset.

(13) DNC Don’t care. This data must be set to 0.

DO Control Data (Serial Data Output) Structure

[3] OUT Mode

DZA

DZB

DZC

DZD

Dead zone mode

0

1

0

1

0

1

DZ0 DZ1

Normal operation

Forced low

0

1

Charge pump output DLC

C1

C2

C3

(2) UNLOCK

(1) IN-PORT

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

(3) IF-CTR

C14

C15

C16

C17

C18

C19

UL



I1

I2

C0

address

Fist Data OUT

0 0 1 0 1 0 1

DO

: Must be 0.

DI 0

F X { MUMMMMMM Umii Jj_ﬂ_ﬂ_ﬂ_ﬂ_ﬂ_ﬂ_ﬂ_ﬂ_ﬂ_?1 , X X X X X X X X X X X vm { U_X_X_ 17 v m X_X_X_X m

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Control Data Functions

No. Control block/data Functions Related data

(1) I/O port data

I2, I1

Latched from the pin states of the IO1 and IO2 I/O ports.

These values follow the pin states regardless of the input or output setting.

I1  IO1 pin state High: 1

I2  IO2 pin state Low: 0

IOC1

IOC2

(2) PLL unlock data

UL

Latched from the state of the unlock detection circuit.

UL  0: Unlocked

UL  1: Locked or detection stopped mode

UL0

UL1

(3) IF counter binary

counter

C19 to C0

Latched from the value of the IF counter (20-bit binary counter).

C19  MSB of the binary counter

C0  LSB of the binary counter

CTE

GT0

GT1

Serial Data I/O Methods

The LC72131K/KMA inputs and outputs data using Our CCB (computer control bus) audio LSI serial bus format. This

LSI adopts an 8-bit address format CCB.

I/O mode

Address

Function

B0 B1 B2 B3 A0 A1 A2 A3

[1] IN1 (82) 0 0 0 1 0 1 0 0

 Control data input mode (serial data input)

 24 data bits are input.

 See the “DI Control Data (serial data input) Structure” item for details

on the meaning of the input data.

[2] IN2 (92) 1 0 0 1 0 1 0 0

 Control data input mode (serial data input)

 24 data bits are input.

 See the “DI Control Data (serial data input) Structure” item for details

on the meaning of the input data.

[3] OUT (A2) 0 1 0 1 0 1 0 0

 Data output mode (serial data output)

 The number of bits output is equal to the number of clock cycles.

 See the “DO Control Data (serial data output) Structure” item for details

on the meaning of the output data.

(2)

(1)

First Data IN1/2

First Data OUT

A3 A2 A1 A0 B3 B2 B1 B0 DI

I/O mode determined

CE

CL



(2)

(1) CL: Normal high

(2) CL: Normal low

(1)

DO

   



 



gmimm XXXXXXXXXXXXXXXXX tES IEH (a

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1. Serial Data Input (IN1/IN2) tSU, tHD, tES, tEH0.75s tLC<0.75s

(1) CL: Normal high

(2) CL: Normal low

2. Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH0.75s tDC, tDH<0.35s

(1) CL: Normal high

(2) CL: Normal low

Note: Since the DO pin is an N-channel open-drain pin, the time for the data to change (tDC and tDH) will differ

depending on the value of the pull-up resistor and printed circuit board capacitance.

Internal data

tLC

tEH tES tEL

tHD tSU

R3 R2 R1 P3 P2 P1 P0 A3 A2 A1 A0 B3 B2 B1 B0 R0 DI

CE

CL

Internal data

tLC

tEH tES tEL

tHD tSU

R3 R2 R1 P3 P2 P1 P0 A3 A2 A1 A0 B3 B2 B1 B0 R0 DI

CE

CL

DO

DI

CE

CL

tDC tDC tDH

tEH tES tEL

tHD tSU

UL I1 I2

A3 A2 A1 A0 B3 B2 B1 B0

C0 C1 C2 C3

DO

tDC tDC tDH

tEH tES tEL

tHD tSU

I1 I2 UL

A3 A2 A1 A0 B3 B2 B1 B0

C0 C1 C2 C3

DI

CE

CL

(A) FMIN 13 1/2 7;] Swallow Counler 1C) 4M7 1 13 ‘3) fvco/N > } 7.}; l T frelj DVS SNS 'V DVS SNS Inpulpm Se|d1v1sur Aclual d1v1sur N 1npu1 irequency range (A) 1 ' FMlN 272 la 55535 TWICE lhe sel value 10 to IEUMHZ (B) 1 1 AMIN 272 la 55535 The sel value 2 in 4UMHZ (C) 0 0 AMIN 4 lo 4095 The sel value 0 5l010MHZ ‘: Don'l care Programmable Divider Calculation Examples (1) (2) (3) FM, 50km slcpx (DVS=1, SNS=*. FMlN sclcclcd) FM RF=90,OMHZ (IF=+1(),7Ml-lz) FM VCO=100.7MH2 PLL frcf=25kHz(Rl)1o 121:1, R2 to R3:<>) ll)l).7MHz (FMVCO)+25kl—lz (frcl) +2 (FMIN: dividcrbyrlwo prcxcalcr) =20144>U7DE (HEX) ,—/%,—/%r—/%r—% sw 514-12 slcpx (DVS=0, SNS=1: AMIN higlrspccd side sclcctcd) sw RF=21.75MH2 (IF=+45()kl-lz) sw VCO=2220MHZ PLL {1's _ kHz (RU=R2=0, Rl=R3-l) 22.2Ml-[z (sw vco; :skHz (m1) #44041 158 (HEX) r—’%r—’%r—’%r—% MW ll)kHz smp. (DVS=U, SNS=0. AMlN lowwccd side sclcctcd) MW RF=1000kHz (IF=+45()kl-lz) MW vc0:1450k112 PLL frcf=10kHz(Rl)1o 122:0, 113:1) 1450kHz (MW vco; 40111-12 (11:11:1454091 (HEX) www.0nsemi.com 15

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15

Programmable Divider Structure

DVS SNS Input pin Set divisor Actual divisor: N Input frequency range

(A)

(B)

(C)

1

0

*

1

0

FMIN

AMIN

272 to 65535

4 to 4095

Twice the set value

The set value

10 to 160MHz

2 to 40MHz

0.5 to 10MHz

*: Don't care

Programmable Divider Calculation Examples

(1) FM, 50kHz steps (DVS=1, SNS=*: FMIN selected)

FM RF=90.0MHz (IF=+10.7MHz)

FM VCO=100.7MHz

PLL fref=25kHz (R0 to R1=1, R2 to R3=0)

100.7MHz (FMVCO)25kHz (fref) 2 (FMIN: divide-by-two prescaler) =201407DE (HEX)

(2) SW 5kHz steps (DVS=0, SNS=1: AMIN high-speed side selected)

SW RF=21.75MHz (IF=+450kHz)

SW VCO=22.20MHz

PLL fref=5kHz (R0=R2=0, R1=R3=1)

22.2MHz (SW VCO) 5kHz (fref) =44401158 (HEX)

(3) MW 10kHz steps (DVS=0, SNS=0: AMIN low-speed side selected)

MW RF=1000kHz (IF=+450kHz)

MW VCO=1450kHz

PLL fref=10kHz (R0 to R2=0, R3=1)

1450kHz (MW VCO) 10kHz (fref)=145091 (HEX)

(A)

(C)

(B)

SNS DVS

4bits 12bits

Swallow

Counter

Programmable

Divider

fvco=frefN

fref

fvco/N

PD E

1/2

FMIN

AMIN

P0

0

P1

0 7 D E

1

P2

1

P3

1

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

SNS

DVS

CTE

XS

R0

R1

R2

R3

1 0 1 1 1 1 1 0 0 0 0 0 * 1 1 1 0 0

P0

0

P1

1 1 5 8

0

P2

0

P3

1

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

SNS

DVS

CTE

XS

R0

R1

R2

R3

1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 0 1

P0

*

P1

0 9 1

*

P2

*

P3

*

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

SNS

DVS

CTE

XS

R0

R1

R2

R3

1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1

(FED IFIN > F TD 3 GT 4/8/32/E4ms ( ) ¢ ¢ GTO GT1 Measurememume GT1 (310 Measurement hme (GT) (ms) Wa1|l1me( o o 4 3w 0 1 5 3w 1 o 32 7w 1 1 54 7w The IF frequency (Fe) i1 mcaxurcd by dclcrmining how many meusuremem perinde GT. CXGT) c: Counl value (number of pulxc IF Counter Frequency Calculation Examples (1) When Ihc measurement period (GT) ix 32m, [he counl IF frcqucncy (Fc) =34240l)+32ms=10 7MHZ (2) When me mcasurcmcnl period (GT) is me, [he counl ( IF frcqucncy (Fc) =360l)+8ms=450kHz www.cnse 16

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IF Counter Structure

The LC72131K/KMA IF counter is a 20-bit binary counter. The result, i.e., the counter’s msb, can be read serially from

the DO pin.

GT1 GT0

Measurement time

Measurement time (GT) (ms) Wait time (twu) (ms)

0

1

0

1

0

1

4

8

32

64

3 to 4

7 to 8

The IF frequency (Fc) is measured by determining how many pulses were input to an IF counter in a specified

measurement period, GT.

Fc= (C=FcGT) C: Count value (number of pulses)

IF Counter Frequency Calculation Examples

(1) When the measurement period (GT) is 32ms, the count (C) is 53980 hexadecimal (342400 decimal):

IF frequency (Fc) =34240032ms=10.7MHz

(2) When the measurement period (GT) is 8ms, the count (C) is E10 hexadecimal (3600 decimal):

IF frequency (Fc) =36008ms=450kHz

4/8/32/64ms

8 to 11 4 to 7 0 to 3

16 to 19 12 to 15

(Fc)

(C)

(GT)

GT0

M

S

B

L

S

B

IF counter

(20bits binary counter)

C=FcGT

CTE

DO pin

GT1

IFIN

C

GT

I2

I1

0 8 9 3 5

UL

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

C0

0 1 0 1 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0

I2

I1

0 1 E 0 0

UL

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

C0

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0

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IF Counter Operation

Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.

The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the

LC72131K/KMA when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the

period between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF

counter at the end of the measurement period must be read out during the period that CTE is 1. This is because the IF

counter is reset when CTE is set to 0.

Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station

detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an

IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is

possible for IF buffer leakage output to cause incorrect stops at points where there is no station.

IFIN minimum input sensitivity standard f [MHz]

IFS 0.4f<0.5 0.5f<8 8f12

1: Normal mode 40mVrms (0.1 to 3mVrms) 40mVrms 40mVrms (1 to 10mVrms)

0: Degradation mode 70mVrms (10 to 15mVrms) 70mVrms 70mVrms (30 to 40mVrms)

Note: Values in parentheses are actual performance values presented as reference data.

Unlock Detection Timing

Unlock Detection Determination Timing

Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,

unlock determination requires a time longer than the period of the reference frequency. However, immediately after

changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the

reference frequency.

Figure 1 Unlocked State Detection Timing

For example, if fref is 1kHz, i.e., the period is 1ms, after changing the divisor N, the system must wait at least 2ms

before checking for the unlocked state.

CTE data=1

Count start Count end (end-UC)

GT

Wait time

Measurement

time

IFIN

Frequncy

Measurement

time

CE

New divisor N’ Old divisor N

New data Old data

Note: After changing the divisor, ERROR

is output after two fref periods.

The divisor N is not updated

during the first period.

N-

counter

ERROR

(unlock)

DATA

LATCH

VCO/N

fref

CE

UNLOCK ﬁ) UNLOCK E detection circuit L W Phase VCO/N comparator .am at DATA LATCH aERROR Figure 2 Circuit Structure W WW —|—F— a Figure 3 Unlocked State Data Output Using Serial Data Output In the LC72131K/KMA, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input (or output) operation is performed At the data output (1) point in Figure 3, although the VCO frequency h tabilized (locked), since no data output has been performed since the div' or N was changed the unlocked state data remains in the unlocked state. As a result, even though the frequency h . ,tabilized (locked). the system remains (from the standpoint of the data) in the unlocked state. Therefore, the unlocked state data acquired at data output (1 ), which occurs immediately after the divisor N was a dummy data output and ignored. The second data output (data output (2)) and following outpuls are valid data. changed, should be treated YES www.0nsemi.com 18

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18

Figure 2 Circuit Structure

Figure 3

Unlocked State Data Output Using Serial Data Output

In the LC72131K/KMA, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a

data input (or output) operation is performed. At the data output (1) point in Figure 3, although the VCO frequency

has stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state

data remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system

remains (from the standpoint of the data) in the unlocked state.

Therefore, the unlocked state data acquired at data output (1), which occurs immediately after the divisor N was

changed, should be treated as a dummy data output and ignored. The second data output (data output (2)) and

following outputs are valid data.

VCO

UNLOCK

L.P.F

ERROR

Phase

comparator

DATA LATCH

N

UNLOCK

detection circuit

R

Preset

VCO/N

fref

Data output (2) Data input Data output (1)

New data Old data

VCO

frequency

Locked Locked Unlocked

ERROR

N

Unlock detection

pin output

Unlock (UL)

serial data output

CE

Valid data can be output at

intervals of one reference

frequency period or longer.

*: Locking state determination is

more reliable if it is based on

reading valid output data several

times

Wait for at least two reference

frequency periods.

Divisor N modification

(

data in

p

ut

)

locked

* NO

YES

Valid data output

Dummy data output

BO! 4i 5 Time base outpul Vcc Loop filter other Items [1| Notes on the Phase Compuralor Dead Zone 021 020 Dead zone mode charge pump 0 o DZA ON/ON o 1 DZB ON/ON I o 020 OFF/OFF I 1 DZD OFF/OFF Since correclion pulses are output from the charge pum ON/ON state, the loop can easily become unslable. Thi circuils. The following problems may occur in the ON/ON slate (1) Side hand generation due I0 reference frequency (2) Side band generation due to both the correction p Schemes in which a dead zone is presenl (OFF/OFF) ha ouiring a high C/N ratio can be oimeuit On lhe othe schemes in which lhere is no dead zone, iI i, ifficull to to select DZA or DZB, which have no dead zone, in ap ”we or in which an increased AM stereo pilot margi me or DZD‘ which provide a dead zone for nppheati ratio and in which eilher AM

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19

Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data)

Since the unlocked state (high=locked, low=unlocked) is output directly from the DO pin, the dummy data

processing described in section 3 above is not required. After changing the divisor N, the locking state can be

checked after waiting at least two reference frequency periods.

Clock Time Base Usage Notes

The pull-up resistor used on the clock time base output pin (BO1) should be at least 100k. This is to prevent

degrading the VCO C/N characteristics when a loop filter is formed using the built-in low-pass filter transistor. Since

the clock time base output pin and the low-pass filter have a common ground internal to the IC, it is necessary to

minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter. Also, to

prevent chattering we recommend using a Schmitt input at the controller (microprocessor) that receives this signal.

Other Items

[1] Notes on the Phase Comparator Dead Zone

DZ1 DZ0 Dead zone mode Charge pump Dead zone

0 0 DZA ON/ON - -0s

0 1 DZB ON/ON -0s

1 0 DZC OFF/OFF +0s

1 1 DZD OFF/OFF ++0s

Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the

ON/ON state, the loop can easily become unstable. This point requires special care when designing application

circuits.

The following problems may occur in the ON/ON state.

(1) Side band generation due to reference frequency leakage

(2) Side band generation due to both the correction pulse envelope and low frequency leakage

Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that

acquiring a high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with

schemes in which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective

to select DZA or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to

100dB, or in which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting

DZC or DZD, which provide a dead zone, for applications which do not require such a high FM signal-to-noise

ratio and in which either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.

VCC

VCO

Vt

VDD

PD

AIN

AOUT

BO1

Rt100k

Schmitt input

Microprocessor

S

LC72131K/KMA

Loop filter

Time base output

:F Reterence Divider a VT 9 a F Programmable Drvrder 7) [2] Notes on the FMlN, AMIN, and [FIN Pins Coupling capacitors must be placed as close as possible to their re desirable in particular, ita capacitance of lOOOpF or over is used will increase and incorrect counting may occur due to the relation [3] Notes on [F CountingaSD must be used in conjunction with the When using [P countingc always iniplenient IF counting by havln the IFVIC SD (station detect) s nal and turn on the IF counter bu which aulonsearches are performed with only 1F counting are not detection where there is no signal due to overﬂow from the IF co [4] DO Pin Usage Techniques In addition to data output mode times, the DO pin can also he use for unlock detection Uulpull Also, an input pin state can he outpu controller. Pin States Alter the Power ON Reset [LC72131K] Open < do="" |:="" lc72131k="" j="" vdd="" open="">< w="" |:="" :‘="" fmin="" open="">< m="" :‘="" amin="" open="">< m="" j="" e="" open="">< h="" e="" j="" m="" e="" input="" part="">< |="" t="" www.0nsemi.colll="" 20="" l="" 7%="" dead="" zane="" %="">

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Dead Zone

The phase comparator compares fp to a reference frequency (fr) as shown in Figure 1. Although the

characteristics of this circuit (see Figure 2) are such that the output voltage is proportional to the phase difference

ø (line A), a region (the dead zone) in which it is not possible to compare small phase differences occurs in actual

ICs due to internal circuit delays and other factors (line B). A dead zone as small as possible is desirable for

products that must provide a high S/N ratio.

However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for

popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and

modulate the VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is

narrow, the circuit outputs correction pulses and this output can further modulate the VCO and generate beat

frequencies with the RF signal.

[2] Notes on the FMIN, AMIN, and IFIN Pins

Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100pF is

desirable. In particular, if a capacitance of 1000pF or over is used for the IF pin, the time to reach the bias level

will increase and incorrect counting may occur due to the relationship with the wait time.

[3] Notes on IF CountingSD must be used in conjunction with the IF counting time

When using IF counting, always implement IF counting by having the microprocessor determine the presence of

the IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in

which auto-searches are performed with only IF counting are not recommended, since they can cause false

detection where there is no signal due to overflow from the IF counter buffer.

[4] DO Pin Usage Techniques

In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and

for unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the

controller.

Pin States After the Power ON Reset [LC72131K]

Reference Divider

VCO LPF

Programmable Divider

Phase

Detector

Figure 1

MIX

RF

Signal leak fr

fp

Figure 2

(ns)

V

(A)

(B)

Dead Zone

Open

VSS

AOUT

AIN

PD

XOUT

VDD

LC72131K

FMIN

AMIN

IO2

IFIN

IO1

BO4

BO3

BO2

BO1

DO

CL

DI

XIN

CE

Input port

Open

Input port

NC

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LC72131K, LC72131KMA

www.onsemi.com

21

Pin States After the Power ON Reset [LC72131KMA]

Application System Example [LC72131K]

Input port

VSS

AOUT

AIN

PD

XOUT

VDD

LC72131KMA

FMIN

AMIN

IO2

IFIN

IO1

BO4

BO3

BO2

BO1

DO

CL

DI

XIN

CE

Open

Input port

Open

2

3

4

5

6

7

8

9

10

11 12

S

LC72131K

VCC

IFIN

AM/FM-IF

TUNER-System

MONO/ST

FM/AM

IF-Request

ST-Indicate

tune

IO1

BO4

BO3

BO2

BO1

DO

CL

DI

CE

XIN

NC

DO

CL

-COM

CE

DI

Unlock

tune

end-UC

IFcount

ST-indic

FMVCO

AMVCO

S

1

13 IO2

14 NC

15 AMIN

16 FMIN

17 VDD

18 PD

19 AIN

20 AOUT

21 VSS

22 XOUT

“.com CE DI CL Umock tune end-UC DO chounl ST-mdwc a T LC72131KMA Eﬁégg Fﬁﬁﬁ a UUUUUUU 9‘ T j}; FVO T ; J AVO 4(97 g 4H— www.0nsemi.com 22

LC72131K, LC72131KMA

www.onsemi.com

22

Application System Example [LC72131KMA]

2

3

4

5

6

7

8

9

10 11

S

LC72131KMA

VCC

IFIN

AM/FM-IF

TUNER-System

MONO/ST

FM/AM

IF-Request

ST-Indicate

tune

IO1

BO4

BO3

BO2

BO1

DO

CL

DI

CE

XIN

DO

CL

-COM

CE

DI

Unlock

tune

end-UC

IFcount

ST-indic

FMVCO

AMVCO

S

1

12 IO2

13 AMIN

14 FMIN

15 VDD

16 PD

17 AIN

18 AOUT

19 VSS

20 XOUT

LC72131K, LC72131KMA

www.onsemi.com

23

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ORDERING INFORMATION

Device Package Shipping (Qty / Packing)

LC72131K-E PDIP22 / DIP22S (300 mil)

(Pb-Free) - / -

LC72131KMA-AE SOIC20W / MFP20J (300 mil)

(Pb-Free) 2000 / Tape & Reel

† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel

Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF

LC72131K/KMA Datasheet by ON Semiconductor

Products related to this Datasheet