MPC5121E, MPC5123 Datasheet by NXP USA Inc.

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0" :o" freescalew semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5121E
Rev. 5, 02/2012
© Freescale Semiconductor, Inc., 2010-2012. All rights reserved.
MPC5121E/MPC5123
516 TEPBGA
27 mm x 27 mm
The MPC5121e/MPC5123 integrates a high performance
e300 CPU core based on the Power Architecture® Technology
with a rich set of peripheral functions focused on
communications and systems integration.
Major features of the MPC5121e/MPC5123 are:
• e300 Power Architecture processor core
• Power modes include doze, nap, sleep, deep sleep, and
hibernate
• AXE – Auxiliary Execution Engine
• MBX Lite – 2D/3D graphics engine (not available in
MPC5123)
• DIU – Display interface unit
• DDR1, DDR2, and LPDDR/mobile-DDR SDRAM
memory controller
• MEM – 128 KB on-chip SRAM
• USB 2.0 OTG controller with integrated physical layer
(PHY)
• DMA subsystem
• EMB – Flexible multi-function external memory bus
interface
• NFC – NAND flash controller
• LPC – LocalPlus interface
• 10/100Base Ethernet
• PCI interface, version 2.3
• PATA – Parallel ATA integrated development environment
(IDE) controller
• SATA – Serial ATA controller with integrated physical
layer (PHY)
• SDHC – MMC/SD/SDIO card host controller
• PSC – Programmable serial controller
•I
2C – inter-integrated circuit communication interfaces
• S/PDIF – Serial audio interface
• CAN – Controller area network
• BDLC – J1850 interface
• VIU – Video Input, ITU-656 compliant
• RTC – On-Chip real-time clock
• On-chip temperature sensor
• IIM – IC Identification module
MPC5121E/MPC5123
Data Sheet
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor2
Table of Contents
1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 516-TEPBGA Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Electrical and Thermal Characteristics . . . . . . . . . . . . . . . . . .17
3.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .17
3.1.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . .17
3.1.2 Recommended Operating Conditions . . . . . . . .18
3.1.3 DC Electrical Specifications. . . . . . . . . . . . . . . .19
3.1.4 Electrostatic Discharge . . . . . . . . . . . . . . . . . . .22
3.1.5 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . .23
3.1.6 Thermal Characteristics. . . . . . . . . . . . . . . . . . .24
3.2 Oscillator and PLL Electrical Characteristics . . . . . . . .25
3.2.1 System Oscillator Electrical Characteristics . . .26
3.2.2 RTC Oscillator Electrical Characteristics. . . . . .26
3.2.3 System PLL Electrical Characteristics. . . . . . . .26
3.2.4 e300 Core PLL Electrical Characteristics . . . . .27
3.3 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .28
3.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.3.2 AC Operating Frequency Data. . . . . . . . . . . . . .28
3.3.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . .32
3.3.5 SDRAM (DDR) . . . . . . . . . . . . . . . . . . . . . . . . .32
3.3.6 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.7 LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.8 NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3.9 PATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.10 SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.3.11 FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.12 USB ULPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.13 On-Chip USB PHY . . . . . . . . . . . . . . . . . . . . . . 60
3.3.14 SDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.15 DIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3.16 SPDIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.17 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.19 J1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.20 PSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.21 GPIOs and Timers . . . . . . . . . . . . . . . . . . . . . . 73
3.3.22 Fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.23 IEEE 1149.1 (JTAG). . . . . . . . . . . . . . . . . . . . . 74
3.3.24 VIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4 System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.1 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . . . . 76
4.2 System and CPU Core AVDD Power Supply Filtering. 76
4.3 Connection Recommendations . . . . . . . . . . . . . . . . . . 77
4.4 Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 78
4.4.1 Pull-Down Resistor Requirements for TEST pin78
4.4.2 Pull-Up Requirements for the PCI Control Lines78
4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5.2 e300 COP / BDM Interface . . . . . . . . . . . . . . . . 79
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 83
6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
<3>>$>> ¢¢¢¢¢ 7‘4 > 77“ ,, > 7, m ,,A c 7, w A 4v A v > J v '11] , :: .. :
Ordering Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 3
Figure 1 shows a simplified MPC5121e/MPC5123 block diagram.
Figure 1. Simplified MPC5121e/MPC5123 Block Diagram
1 Ordering Information
Table 1. MPC5121e Orderable Part Numbers
Freescale Part Number Speed (MHz) Temperature
(ambient) Qualification Package Availability
MPC5121VY400B 400 0 oC to 70 oCConsumer RoHS and Pb-free Tray
MPC5121VY400BR 400 0 oC to 70 oCConsumer RoHS and Pb-free Tape and Reel
MPC5121YVY400B 400 –40 oC to 85 oCIndustrial RoHS and Pb-free Tray
MPC5121YVY400BR 400 –40 oC to 85 oCIndustrial RoHS and Pb-free Tape and Reel
SPC5121YVY400B 400 –40 oC to 85 oCAutomotive—AEC RoHS and Pb-free Tray
SPC5121YVY400BR 400 –40 oC to 85 oCAutomotive—AEC RoHS and Pb-free Tape and Reel
Table 2. MPC5123 Orderable Part Numbers
Freescale Part Number Speed (MHz) Temperature
(ambient) Qualification Package Availability
MPC5123VY400B 400 0 oC to 70 oCConsumer RoHS and Pb-free Tray
MPC5123VY400BR 400 0 oC to 70 oCConsumer RoHS and Pb-free Tape and Reel
MPC5123YVY400B 400 –40 oC to 85 oCIndustrial RoHS and Pb-free Tray
PMC
IPIC
WDT
GPT
GPIO
I2C×3
CAN × 4
J1850
SDHC
SPDIF
CFM
PSC × 12
RTC
83 MHz (max) IP Bus
Display
DDR1/DDR2 Memory
Functionally
Multiplexed I/O
LPC
NFC
PATA
EMB
83 MHz IP Bus
AXE
Engine
8KB
DIU
Multi-Port
Memory Controller
MBX Lite
Graphics Engine with
Vector Processing
FEC
USB2
+ PHY
USB2
ULPI
SATA
+ PHY
PCI
200 MHz AHB (32-bit)
Temp Fuse
128 KB
SRAM
DMA
64-Channel
e300
Power Architecture
32 KB Instruction Cache
32 KB Data Cache
200 MHz CSB
Bus (64-bit)
RESET/
JTAG/COP
CLOCK
Instruc-
VIU
not available in MPC5123
tion
Cache
MPC5121E/MPC5123 Data Sheet, Rev. 5
Ordering Information
Freescale Semiconductor4
MPC5123YVY400BR 400 –40 oC to 85 oCIndustrial RoHS and Pb-free Tape and Reel
SPC5123YVY400B 400 –40 oC to 85 oCAutomotive—AEC RoHS and Pb-free Tray
SPC5123YVY400BR 400 –40 oC to 85 oCAutomotive—AEC RoHS and Pb-free Tape and Reel
Table 2. MPC5123 Orderable Part Numbers (continued)
Freescale Part Number Speed (MHz) Temperature
(ambient) Qualification Package Availability
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 5
2 Pin Assignments
This section details pin assignments.
2.1 516-TEPBGA Ball Map
Figure 2. Ball Map for the MPC5121e 516 TEPBGA Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
AVSS VSS SATA_
RXN SATA_
RXP
SATA_
RX_VS
SA
PSC7_
4PSC7_
3PSC6_
4PSC6_
2PSC6_
0PSC11
_0 PSC10
_2 PSC2_
3PSC1_
3PSC1_
1PSC0_
1CAN1_
TX GPIO2
8RTC_X
TALO
USB2_
DRVVB
US
USB_D
MUSB_D
PUSB_T
PA VSS
BVSS VSS VSS SATA_
RX_VS
SA VSS PSC8_
3VSS PSC7_
0PSC6_
3VDD_I
OPSC11
_1 VSS PSC10
_1 PSC2_
1VDD_I
OPSC0_
4VSS GPIO3
1CAN2_
RX VSS
USB2_
VBUS_
PWR_F
AULT
VSS USB_V
SSA_B
IAS
USB_X
TALO VDD_I
OVSS
CVSS SATA_
XTALO SATA_
XTALI VSS SATA_
VDDA_
1P2
PSC9_
0PSC8_
2PSC7_
2
AVDD_
FUSE
WR
PSC6_
1PSC11
_2 PSC10
_3 PSC10
_0 PSC2_
0PSC1_
0PSC0_
3
PSC_
MCLK_
IN
GPIO3
0CAN1_
RX RTC_X
TAL I USB_V
DDA USB_V
SSA VSS USB_X
TAL I VSS PCI_C
LK
DSATA_
VDDA_
1P2 VSS SATA_
PLL_V
SSA
SATA_
VDDA_
3P3
SATA_
VDDA_
VREG
PSC9_
3PSC9_
1PSC8_
1VDD_I
OVDD_I
OPSC11
_4 VSS PSC2_
4PSC1_
4VDD_I
OPSC0_
0VSS HIB_M
ODE VBAT_
RTC USB_V
DDA USB_V
BUS
USB_V
DDA_B
IAS
USB_P
LL_PW
R3 VSS VSS PCI_R
EQ2
ESATA_
TXN
SATA_V
DDA_1
P2
SATA_P
LL_VDD
A1P2
SATA_R
ESREF
SATA_A
NAVIZ
PSC9_
4PSC9_
2PSC8_
4PSC8_
0PSC7_
1PSC11
_3 PSC10
_4 PSC2_
2PSC1_
2PSC0_
2CAN2_
TX GPIO2
9VSS USB_U
ID USB_V
SSA USB_V
SSA USB_R
REF
USB_PL
L_GND
PCI_G
NT2 PCI_G
NT0 PCI_R
EQ1
FSATA_
TXP VSS VSS VSS VSS VSS VSS VSS VDD_I
OVDD_I
OVDD_I
OVSS VSS VDD_I
OVSS
PCI_RS
T_OUT
VDD_I
OPCI_A
D30 VDD_I
OPCI_A
D28
GSATA_
TX_VS
SA
NFC_R
ENFC_
WE NFC_
WP VSS PCI_G
NT1 PCI_R
EQ0 PCI_A
D29 PCI_A
D26 PCI_C/
BE3
HNFC_R
/BPATA_
DACK NFC_C
E0 NFC_A
LE NFC_C
LE VSS VDD_I
OPCI_A
D31 VSS PCI_A
D24 VSS PCI_A
D21
JPATA_I
OR
PATA_ I
OCHR
DY
PATA_I
NTRQ PATA_
DRQ VDD_I
OPCI_A
D27 PCI_A
D25 PCI_A
D23 PCI_A
D20 PCI_A
D18
KPATA_
CE1 VDD_I
O
PATA_I
SOLAT
E
VDD_I
OPATA_ I
OW VSS VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VSS PCI_ID
SEL PCI_A
D22 PCI_A
D19 PCI_A
D17 PCI_IR
DY
LEMB_A
D03 EMB_A
D02 EMB_A
D01 EMB_A
D00 PATA_
CE2 VSS VDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE VSS PCI_A
D16 VDD_I
OPCI_C/
BE2VDD_I
OPCI_D
EVSEL
MEMB_A
D06 VSS EMB_A
D05 VSS EMB_A
D04 VDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE PCI_T
RDY PCI_F
RAME PCI_S
TOP PCI_P
ERR PCI_S
ERR
NEMB_A
D10 EMB_A
D09 EMB_A
D08 EMB_A
D07 VSS VDD_I
OVDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE VDD_I
OPCI_P
AR VSS PCI_C/
BE1VSS PCI_A
D15
PEMB_A
D15 EMB_A
D14 EMB_A
D11 EMB_A
D13 EMB_A
D12 VDD_I
OVDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE VDD_I
OPCI_C/
BE0PCI_A
D09 PCI_A
D13 PCI_A
D14 PCI_A
D12
REMB_A
D17 VDD_I
OEMB_A
D16 VDD_I
OEMB_A
D19 VDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE PCI_A
D03 PCI_A
D06 PCI_A
D10 PCI_A
D11 PCI_A
D08
TEMB_A
D22 EMB_A
D18 EMB_A
D20 EMB_A
D21 EMB_A
D23 VSS VDD_C
ORE VSS VSS VSS VSS VSS VSS VDD_C
ORE VSS
SYS_PL
L_AVDD
VDD_I
OPCI_A
D05 VDD_I
OPCI_A
D07
UEMB_A
D25 VSS EMB_A
D24 VSS EMB_A
D29 VSS VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VDD_C
ORE VSS
SYS_PL
L_AVSS
PCI_IN
TA PCI_A
D00 PCI_A
D02 PCI_A
D04
VEMB_A
D26 EMB_A
D27 EMB_A
D28 EMB_A
D30 EMB_A
X01 SRESE
TVSS SYS_X
TAL I VSS PCI_A
D01
WEMB_A
D31 EMB_A
X00 EMB_A
X02 LPC_A
X03 LPC_C
S0 VDD_I
OVDD_I
OTDO PORE
SET HRES
ET TEST SYS_X
TALO
YLPC_C
S2 VDD_I
OLPC_C
S1 VDD_I
OLPC_O
EJ1850_
TX TDI VSS TMS CKSTP
_OUT
AA LPC_R
WB LPC_A
CK PSC4_
1LPC_C
LK PSC4_
3VSS VDD_
MEM_I
OVSS VSS VDD_
MEM_I
O
VDD_
MEM_I
OVSS VSS CORE
_PLL_
AVDD VSS I2C2_S
DA VDD_I
OJ1850_
RX VDD_I
OTRST
AB PSC4_
0VSS PSC4_
2VSS PSC3_
1MDQ1 MVTT0 MDQ5 MDQ1
0VSS MVRE
FMDQ1
9MDQ2
1MDQ2
7MDQ3
1MA1 MA5 VDD_
MEM_I
OMA14 MCKE SPDIF
_TXCL
K
I2C1_S
CL I2C1_S
DA VSS IRQ1 TCK
AC PSC5_
0PSC4_
4PSC5_
1PSC3_
2
VDD_
MEM_I
OMDM0 MDQ8 VSS MDQ1
4
VDD_
MEM_I
O
MDQS
2VSS MDQ2
5
VDD_
MEM_I
O
MDQ3
0MBA1 VSS MA7 MA11 VDD_
MEM_I
OMODT VSS I2C0_S
CL SPDIF
_RX I2C2_S
CL IRQ0
AD PSC5_
2PSC5_
3VSS PSC3_
3MDQS
0MDQ6 MDQ1
1MDQS
1
VDD_
MEM_I
O
MDQ1
6MDQ1
8MDQ2
0MDQ2
3MDQS
3MDQ2
9MBA0 MA0 MA4 MA9 MA13 MWE MCS CORE
_PLL_
AVSS
SPDIF
_TX VSS I2C0_S
DA
AE VDD_I
OVDD_I
OPSC5_
4MDQ2 VDD_
MEM_I
OMDQ7 VSS MDM1 MDQ1
2
VDD_
MEM_I
OMVTT2 VSS MDQ2
4MVTT3 VDD_
MEM_I
O
MDQ2
8VSS MA2 MA6 VDD_
MEM_I
OMA12 MA15 VSS VDD_I
OVDD_I
OVSS
AF VDD_I
OPSC3_
0PSC3_
4MDQ0 MDQ3 MDQ4 MDQ9 MVTT1 MDQ1
3MDQ1
5MDQ1
7MDM2 MDQ2
2MDQ2
6MDM3 MCK MCK MBA2 MA3 MA8 MA10 MRAS MCAS VDD_I
O
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor6
2.2 Pinout Listings
Table 3 provides the pin-out listing for the MPC5121e/MPC5123.
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 1 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
DDR Memory Interface (67 Total)
MDQ0 AF5 DDR
V
DD_MEM_IO
—
MDQ1 AB6 DDR
V
DD_MEM_IO
—
MDQ2 AE4 DDR
V
DD_MEM_IO
—
MDQ3 AF6 DDR
V
DD_MEM_IO
—
MDQ4 AF7 DDR
V
DD_MEM_IO
—
MDQ5 AB8 DDR
V
DD_MEM_IO
—
MDQ6 AD6 DDR
V
DD_MEM_IO
—
MDQ7 AE6 DDR
V
DD_MEM_IO
—
MDQ8 AC7 DDR
V
DD_MEM_IO
—
MDQ9 AF8 DDR
V
DD_MEM_IO
—
MDQ10 AB9 DDR
V
DD_MEM_IO
—
MDQ11 AD7 DDR
V
DD_MEM_IO
—
MDQ12 AE9 DDR
V
DD_MEM_IO
—
MDQ13 AF10 DDR
V
DD_MEM_IO
—
MDQ14 AC9 DDR
V
DD_MEM_IO
—
MDQ15 AF11 DDR
V
DD_MEM_IO
—
MDQ16 AD10 DDR
V
DD_MEM_IO
—
MDQ17 AF12 DDR
V
DD_MEM_IO
—
MDQ18 AD11 DDR
V
DD_MEM_IO
—
MDQ19 AB12 DDR
V
DD_MEM_IO
—
MDQ20 AD12 DDR
V
DD_MEM_IO
—
MDQ21 AB13 DDR
V
DD_MEM_IO
—
MDQ22 AF14 DDR
V
DD_MEM_IO
—
MDQ23 AD13 DDR
V
DD_MEM_IO
—
MDQ24 AE13 DDR
V
DD_MEM_IO
—
MDQ25 AC13 DDR
V
DD_MEM_IO
—
MDQ26 AF15 DDR
V
DD_MEM_IO
—
MDQ27 AB14 DDR
V
DD_MEM_IO
—
MDQ28 AE16 DDR
V
DD_MEM_IO
—
MDQ29 AD15 DDR
V
DD_MEM_IO
—
MDQ30 AC15 DDR
V
DD_MEM_IO
—
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 7
MDQ31 AB15 DDR
V
DD_MEM_IO
—
MDM0 AC6 DDR
V
DD_MEM_IO
—
MDM1 AE8 DDR
V
DD_MEM_IO
—
MDM2 AF13 DDR
V
DD_MEM_IO
—
MDM3 AF16 DDR
V
DD_MEM_IO
—
MDQS0 AD5 DDR
V
DD_MEM_IO
—
MDQS1 AD8 DDR
V
DD_MEM_IO
—
MDQS2 AC11 DDR
V
DD_MEM_IO
—
MDQS3 AD14 DDR
V
DD_MEM_IO
—
MBA0 AD16 DDR
V
DD_MEM_IO
—
MBA1 AC16 DDR
V
DD_MEM_IO
—
MBA2 AF19 DDR
V
DD_MEM_IO
—
MA0 AD17 DDR
V
DD_MEM_IO
—
MA1 AB16 DDR
V
DD_MEM_IO
—
MA2 AE18 DDR
V
DD_MEM_IO
—
MA3 AF20 DDR
V
DD_MEM_IO
—
MA4 AD18 DDR
V
DD_MEM_IO
—
MA5 AB17 DDR
V
DD_MEM_IO
—
MA6 AE19 DDR
V
DD_MEM_IO
—
MA7 AC18 DDR
V
DD_MEM_IO
—
MA8 AF21 DDR
V
DD_MEM_IO
—
MA9 AD19 DDR
V
DD_MEM_IO
—
MA10 AF22 DDR
V
DD_MEM_IO
—
MA11 AC19 DDR
V
DD_MEM_IO
—
MA12 AE21 DDR
V
DD_MEM_IO
—
MA13 AD20 DDR
V
DD_MEM_IO
—
MA14 AB19 DDR
V
DD_MEM_IO
—
MA15 AE22 DDR
V
DD_MEM_IO
—
MWE AD21 DDR
V
DD_MEM_IO
—
MRAS AF23 DDR
V
DD_MEM_IO
—
MCAS AF24 DDR
V
DD_MEM_IO
—
MCS AD22 DDR
V
DD_MEM_IO
—
MCKE AB20 DDR
V
DD_MEM_IO
—
MCK AF17 DDR
V
DD_MEM_IO
—
MCK AF18 DDR
V
DD_MEM_IO
—
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 2 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor8
MODT AC21 DDR
V
DD_MEM_IO
—
LPC Interface (8 Total)
LPC_CLK AA4 General IO VDD_IO —
LPC_OE Y5 General IO VDD_IO —
LPC_RWAA1 General IO VDD_IO —
LPC_CS0 W5 General IO VDD_IO —
LPC_CS1 Y3 General IO VDD_IO —
LPC_CS2 Y1 General IO VDD_IO —
LPC_ACK AA2 General IO VDD_IO —
LPC_AX03 W4 General IO VDD_IO —
EMB Interface (35 Total)
EMB_AX02 W3 General IO VDD_IO —
EMB_AX01 V5 General IO VDD_IO —
EMB_AX00 W2 General IO VDD_IO —
EMB_AD31 W1 General IO VDD_IO —
EMB_AD30 V4 General IO VDD_IO —
EMB_AD29 U5 General IO VDD_IO —
EMB_AD28 V3 General IO VDD_IO —
EMB_AD27 V2 General IO VDD_IO —
EMB_AD26 V1 General IO VDD_IO —
EMB_AD25 U1 General IO VDD_IO —
EMB_AD24 U3 General IO VDD_IO —
EMB_AD23 T5 General IO VDD_IO —
EMB_AD22 T1 General IO VDD_IO —
EMB_AD21 T4 General IO VDD_IO —
EMB_AD20 T3 General IO VDD_IO —
EMB_AD19 R5 General IO VDD_IO —
EMB_AD18 T2 General IO VDD_IO —
EMB_AD17 R1 General IO VDD_IO —
EMB_AD16 R3 General IO VDD_IO —
EMB_AD15 P1 General IO VDD_IO —
EMB_AD14 P2 General IO VDD_IO —
EMB_AD13 P4 General IO VDD_IO —
EMB_AD12 P5 General IO VDD_IO —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 3 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 9
EMB_AD11 P3 General IO VDD_IO —
EMB_AD10 N1 General IO VDD_IO —
EMB_AD09 N2 General IO VDD_IO —
EMB_AD08 N3 General IO VDD_IO —
EMB_AD07 N4 General IO VDD_IO —
EMB_AD06 M1 General IO VDD_IO —
EMB_AD05 M3 General IO VDD_IO —
EMB_AD04 M5 General IO VDD_IO —
EMB_AD03 L1 General IO VDD_IO —
EMB_AD02 L2 General IO VDD_IO —
EMB_AD01 L3 General IO VDD_IO —
EMB_AD00 L4 General IO VDD_IO —
PATA Interface (9 Total)
PATA_CE1 K1 General IO VDD_IO ATA name: CS0
PATA_CE2 L5 General IO VDD_IO ATA name: CS1
PATA_ISOLATE K3 General IO VDD_IO —
PATA_IOR J1 General IO VDD_IO ATA name: DIOR
PATA_IOW K5 General IO VDD_IO ATA name: DIOW
PATA_IOCHRDY J2 General IO VDD_IO ATA name: IORDY
PATA_INTRQ J3 General IO VDD_IO —
PATA_DRQ J4 General IO VDD_IO ATA name: DMARQ
PATA_DACK H2 General IO VDD_IO ATA name: DMACK
NFC Interface (7 Total)
NFC_WP G4 General IO VDD_IO —
NFC_R/BH1 General IO VDD_IO —
NFC_WE G3 General IO VDD_IO —
NFC_RE G2 General IO VDD_IO —
NFC_ALE H4 General IO VDD_IO —
NFC_CLE H5 General IO VDD_IO —
NFC_CE0 H3 General IO VDD_IO —
I2C Interface (6 Total)
I2C0_SCL AC23 General IO VDD_IO —
I2C0_SDA AD26 General IO VDD_IO —
I2C1_SCL AB22 General IO VDD_IO —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 4 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor10
I2C1_SDA AB23 General IO VDD_IO —
I2C2_SCL AC25 General IO VDD_IO —
I2C2_SDA AA22 General IO VDD_IO —
IRQ Interface (2 Total)
IRQ0 AC26 General IO VDD_IO —
IRQ1 AB25 General IO VDD_IO —
CAN Interface (4 Total)
CAN1_RX C19 Analog Input VBAT_RTC —
CAN1_TX A18 General IO VDD_IO —
CAN2_RX B19 Analog Input VBAT_RTC —
CAN2_TX E16 General IO VDD_IO —
J1850 Interface (2 Total)
J1850_TX Y22 General IO VDD_IO —
J1850_RX AA24 General IO VDD_IO —
SPDIF Interface (3 Total)
SPDIF_TXCLK AB21 General IO VDD_IO —
SPDIF_TX AD24 General IO VDD_IO —
SPDIF_RX AC24 General IO VDD_IO —
PCI (54 Total)
PCI_INTA U23 PCI VDD_IO —
PCI_RST_OUT F22 PCI VDD_IO —
PCI_AD00 U24 PCI VDD_IO —
PCI_AD01 V26 PCI VDD_IO —
PCI_AD02 U25 PCI VDD_IO —
PCI_AD03 R22 PCI VDD_IO —
PCI_AD04 U26 PCI VDD_IO —
PCI_AD05 T24 PCI VDD_IO —
PCI_AD06 R23 PCI VDD_IO —
PCI_AD07 T26 PCI VDD_IO —
PCI_AD08 R26 PCI VDD_IO —
PCI_AD09 P23 PCI VDD_IO —
PCI_AD10 R24 PCI VDD_IO —
PCI_AD11 R25 PCI VDD_IO —
PCI_AD12 P26 PCI VDD_IO —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 5 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 11
PCI_AD13 P24 PCI VDD_IO —
PCI_AD14 P25 PCI VDD_IO —
PCI_AD15 N26 PCI VDD_IO —
PCI_AD16 L22 PCI VDD_IO —
PCI_AD17 K25 PCI VDD_IO —
PCI_AD18 J26 PCI VDD_IO —
PCI_AD19 K24 PCI VDD_IO —
PCI_AD20 J25 PCI VDD_IO —
PCI_AD21 H26 PCI VDD_IO —
PCI_AD22 K23 PCI VDD_IO —
PCI_AD23 J24 PCI VDD_IO —
PCI_AD24 H24 PCI VDD_IO —
PCI_AD25 J23 PCI VDD_IO —
PCI_AD26 G25 PCI VDD_IO —
PCI_AD27 J22 PCI VDD_IO —
PCI_AD28 F26 PCI VDD_IO —
PCI_AD29 G24 PCI VDD_IO —
PCI_AD30 F24 PCI VDD_IO —
PCI_AD31 H22 PCI VDD_IO —
PCI_C/BE0P22 PCI VDD_IO —
PCI_C/BE1N24 PCI VDD_IO —
PCI_C/BE2L24 PCI VDD_IO —
PCI_C/BE3G26 PCI VDD_IO —
PCI_PAR N22 PCI VDD_IO —
PCI_FRAME M23 PCI VDD_IO 1
PCI_TRDY M22 PCI VDD_IO 1
PCI_IRDY K26 PCI VDD_IO 1
PCI_STOP M24 PCI VDD_IO 1
PCI_DEVSEL L26 PCI VDD_IO 1
PCI_IDSEL K22 PCI VDD_IO —
PCI_SERR M26 PCI VDD_IO 1
PCI_PERR M25 PCI VDD_IO 1
PCI_REQ0 G23 PCI VDD_IO 1
PCI_REQ1 E26 PCI VDD_IO 1
PCI_REQ2 D26 PCI VDD_IO 1
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 6 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor12
PCI_GNT0 E25 PCI VDD_IO —
PCI_GNT1 G22 PCI VDD_IO —
PCI_GNT2 E24 PCI VDD_IO —
PCI_CLK C26 PCI VDD_IO —
PSC Interface (61 Total)
PSC_MCLK_IN C17 General IO VDD_IO —
PSC0_0 D16 General IO VDD_IO —
PSC0_1 A17 General IO VDD_IO —
PSC0_2 E15 General IO VDD_IO —
PSC0_3 C16 General IO VDD_IO —
PSC0_4 B16 General IO VDD_IO —
PSC1_0 C15 General IO VDD_IO —
PSC1_1 A16 General IO VDD_IO —
PSC1_2 E14 General IO VDD_IO —
PSC1_3 A15 General IO VDD_IO —
PSC1_4 D14 General IO VDD_IO —
PSC2_0 C14 General IO VDD_IO —
PSC2_1 B14 General IO VDD_IO —
PSC2_2 E13 General IO VDD_IO —
PSC2_3 A14 General IO VDD_IO —
PSC2_4 D13 General IO VDD_IO —
PSC3_0 AF3 General IO VDD_IO —
PSC3_1 AB5 General IO VDD_IO —
PSC3_2 AC4 General IO VDD_IO —
PSC3_3 AD4 General IO VDD_IO —
PSC3_4 AF4 General IO VDD_IO —
PSC4_0 AB1 General IO VDD_IO —
PSC4_1 AA3 General IO VDD_IO —
PSC4_2 AB3 General IO VDD_IO —
PSC4_3 AA5 General IO VDD_IO —
PSC4_4 AC2 General IO VDD_IO —
PSC5_0 AC1 General IO VDD_IO —
PSC5_1 AC3 General IO VDD_IO —
PSC5_2 AD1 General IO VDD_IO —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 7 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 13
PSC5_3 AD2 General IO VDD_IO —
PSC5_4 AE3 General IO VDD_IO —
PSC6_0 A11 General IO VDD_IO —
PSC6_1 C10 General IO VDD_IO —
PSC6_2 A10 General IO VDD_IO —
PSC6_3 B9 General IO VDD_IO —
PSC6_4 A9 General IO VDD_IO —
PSC7_0 B8 General IO VDD_IO —
PSC7_1 E10 General IO VDD_IO —
PSC7_2 C8 General IO VDD_IO —
PSC7_3 A8 General IO VDD_IO —
PSC7_4 A7 General IO VDD_IO —
PSC8_0 E9 General IO VDD_IO —
PSC8_1 D8 General IO VDD_IO —
PSC8_2 C7 General IO VDD_IO —
PSC8_3 B6 General IO VDD_IO —
PSC8_4 E8 General IO VDD_IO —
PSC9_0 C6 General IO VDD_IO —
PSC9_1 D7 General IO VDD_IO —
PSC9_2 E7 General IO VDD_IO —
PSC9_3 D6 General IO VDD_IO —
PSC9_4 E6 General IO VDD_IO —
PSC10_0 C13 General IO VDD_IO —
PSC10_1 B13 General IO VDD_IO —
PSC10_2 A13 General IO VDD_IO —
PSC10_3 C12 General IO VDD_IO —
PSC10_4 E12 General IO VDD_IO —
PSC11_0 A12 General IO VDD_IO —
PSC11_1 B11 General IO VDD_IO —
PSC11_2 C11 General IO VDD_IO —
PSC11_3 E11 General IO VDD_IO —
PSC11_4 D11 General IO VDD_IO —
JTAG (5 Total)
TCK AB26 General IO VDD_IO 2
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 8 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor14
TDI Y23 General IO VDD_IO 3
TDO W22 General IO VDD_IO —
TMS Y25 General IO VDD_IO 3
TRST AA26 General IO VDD_IO 3
Test / Debug (2 Total)
TEST W25 General IO VDD_IO 4, 5
CKSTP_OUT Y26 General IO VDD_IO —
System Control (3 Total)
HRESET W24 General IO VDD_IO 6, 2
PORESET W23 General IO VDD_IO 4, 2
SRESET V22 General IO VDD_IO 6, 2
System Clock (2 Total)
SYS_XTALI V24 Analog Input SYS_PLL_AVDD Oscillator Input
SYS_XTALO W26 Analog Output SYS_PLL_AVDD Oscillator Output
RTC (3 Total)
RTC_XTALI C20 Analog Input VBAT_RTC Oscillator Input
RTC_XTALO A20 Analog Output VBAT_RTC Oscillator Output
HIB_MODE D18 Analog Output VBAT_RTC —
GP Input Only (4 Total)
GPIO28 A19 Analog Input VBAT_RTC —
GPIO29 E17 Analog Input VBAT_RTC —
GPIO30 C18 Analog Input VBAT_RTC —
GPIO31 B18 Analog Input VBAT_RTC —
DDR Reference Voltage
MVREF AB11 Analog Input Voltage Reference for SSTL input pads
USB – PHY without Power and Ground Supplies (7 Total)
USB_XTALI C24 Analog Input USB_PLL_PWR3 Oscillator Input
USB_XTALO B24 Analog Output USB_PLL_PWR3 Oscillator Output
USB_DP A23 Analog IO USB_VDDA —
USB_DM A22 Analog IO USB_VDDA —
USB_TPA A24 Analog Output —USB PHY
debug output
USB_VBUS D21 Analog IO — —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 9 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 15
USB_UID E19 Analog Input — —
USB digital IOs (2 Total)
USB2_VBUS_PWR_FA
ULT B21 General IO VDD_IO —
USB2_DRVVBUS A21 General IO VDD_IO —
SATA PHY without Power and Ground Supplies (7 Total)
SATA_XTALI C3 Analog Input SATA_VDDA_3P3 Oscillator Input
SATA_XTALO C2 Analog Output SATA_VDDA_3P3 Oscillator Output
SATA_ANAVIZ E5 Analog Output —SATA PHY debug
output
SATA_TXN E1 Analog Output SATA_VDDA_1P2 —
SATA_TXP F1 Analog Output SATA_VDDA_1P2 —
SATA_RXP A5 Analog Input SATA_VDDA_1P2 —
SATA_RXN A4 Analog Input SATA_VDDA_1P2 —
Power and Ground Supplies (without SATA PHY and USB PHY)
VDD_CORE K10, K11, K12, K13,
K14, K15, K16, K17,
L10, L17, M10, M17,
N10, N17, P10, P17,
R10, R17, T10, T17,
U10, U11, U12, U13,
U14, U15, U16, U17
Power — —
VDD_IO B10, B15, B25, D9,
D10, D15, F11, F13,
F14, F19, F23, F25,
H21, J5, K2, K4, L23,
L25, N6, N21, P6,
P21, R2, R4, T23,
T25, W6, W21, Y2,
Y4, AA23, AA25, AE1,
AE2, AE24, AE25,
AF2, AF25
Power — —
V
DD_MEM_IO
AA8, AA13, AA14,
AB18, AC5, AC10,
AC14, AC20, AD9,
AE5, AE10, AE15,
AE20
Power — —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 10 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Pin Assignments
Freescale Semiconductor16
VSS A2, A3, A25, B1,B2,
B3, B5, B7, B12, B17,
B20, B22, B26, C1,
C4, C23, C25, D2,
D12, D17, D24, D25,
E18, F2, F3, F4, F5,
F6, F8, F10, F16, F17,
F21, G5, H6, H23,
H25, K6, K21, L6, L11,
L12, L13, L14, L15,
L16, L21, M2, M4,
M11, M12, M13, M14,
M15, M16, N5, N11,
N12, N13, N14, N15,
N16,
Ground — —
VSS N23, N25, P11, P12,
P13, P14, P15, P16,
R11, R12, R13, R14,
R15, R16, T6, T11,
T12, T13, T14, T15,
T16, T21, U2, U4, U6,
U21, V23, V25, Y24,
AA6, AA10, AA11,
AA16, AA17, AA21,
AB2, AB4, AB10,
AB24, AC8, AC12,
AC17, AC22, AD3,
AD25, AE7, AE12,
AE17, AE23, AE26
Ground — —
SYS_PLL_AVDD T22 Analog Power — —
SYS_PLL_AVSS U22 Analog Ground — —
CORE_PLL_AVDD AA19 Analog Power — —
CORE_PLL_AVSS AD23 Analog Ground — —
VBAT_RTC D19 Power — —
AVDD_FUSEWR C9 Power — —
MVTT0 AB7 Analog Input SSTL(DDR2) Termination (ODT) Voltage
MVTT1 AF9 Analog Input SSTL(DDR2) Termination (ODT) Voltage
MVTT2 AE11 Analog Input SSTL(DDR2) Termination (ODT) Voltage
MVTT3 AE14 Analog Input SSTL(DDR2) Termination (ODT) Voltage
Power and Ground Supplies (USB PHY)
USB_PLL_GND E23 Analog Ground — —
USB_PLL_PWR3 D23 Analog Power — —
USB_RREF E22 Analog Power — —
USB_VSSA_BIAS B23 Analog Ground — —
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 11 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
Pin Assignments
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 17
NOTE
This table indicates only the pins with permananently enabled internal pull-up, pull-down,
or Schmitt trigger. Most of the digital I/O pins can be configured to enable internal pull-up,
pull-down, or Schmitt trigger. See the MPC5121e Microcontroller Reference Manual, IO
Control chapter.
USB_VDDA_BIAS D22 Analog Power — —
USB_VSSA C22, E20, E21 Analog Ground — —
USB_VDDA C21, D20 Analog Power — —
Power and Ground Supplies (SATA PHY)
SATA_RESREF E4 Analog Power — —
SATA_VDDA_3P3 D4 Analog Power — —
SATA_VDDA_1P2 C5, D1, E2 Analog Power — —
SATA_VDDA_VREG D5 Analog Power — —
SATA_PLL_VDDA1P2 E3 Analog Power — —
SATA_PLL_VSSA D3 Analog Ground — —
SATA_RX_VSSA A6, B4 Analog Ground — —
SATA_TX_VSSA G1 Analog Ground — —
1This pins should have an external pull-up resistor. Follow PCI specification and see System Design
Information.
2This pin contains an enabled internal Schmitt trigger.
3These JTAG pins have internal pull-up P-FETs. This pin can not be configured.
4This pin is an input only. This pin can not be configured.
5This test pin must be tied to VSS.
6This pin is an input or open-drain output. This pin can not be configured. There is an internal pull-up resistor
implemented.
Table 3. MPC5121e/MPC5123 TE-PBGA Pinout Listing (Sheet 12 of 12)
Signal Package Pin Number Pad Type Power Supply Notes
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor18
3 Electrical and Thermal Characteristics
3.1 DC Electrical Characteristics
3.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC5121e/MPC5123 DC Electrical characteristics. Table 4 gives the absolute maximum
ratings.
Table 4. Absolute Maximum Ratings1
1Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses
beyond those listed may affect device reliability or cause permanent damage.
Characteristic Symbol Min Max Unit SpecID
Supply voltage – e300 core and peripheral logic VDD_CORE –0.3 1.47 VD1.1
Supply voltage – I/O buffers VDD_IO,
V
DD_MEM_IO
–0.3 3.6 VD1.2
Input reference voltage (DDR/DDR2) MVREF –0.3 3.6 V
Termination Voltage (DDR2) MVTT –0.3 3.6 V
Supply voltage – System APLL, System Oscillator SYS_PLL_AVDD –0.3 3.6 VD1.3
Supply voltage – e300 APLL CORE_PLL_AVDD –0.3 3.6 VD1.4
Supply voltage – RTC (Hibernation) VBAT_RTC –0.3 3.6 VD1.5
Supply voltage – FUSE Programming AVDD_FUSEWR –0.3 3.6 VD1.6
Supply voltage – SATA PHY analog SATA_VDDA_3P3 –0.3 3.6 VD1.8
Supply voltage – SATA PHY voltage regulator SATA_VDDA_VREG –0.3 2.6 VD1.9
Supply voltage – SATA PHY Tx/Rx SATA_VDDA_1P2 –0.3 1.47 VD1.10
Supply voltage – SATA PHY PLL SATA_PLL_VDDA1P2 –0.3 1.47 VD1.11
Supply voltage – USB PHY PLL and OSC USB_PLL_PWR3 –0.3 3.6 VD1.12
Supply voltage – USB PHY transceiver USB_VDDA –0.3 3.6 VD1.13
Supply voltage – USB PHY bandgap bias USB_VDDA_BIAS –0.3 3.6 VD1.14
Input voltage – USB PHY cable USB_VBUS –0.3 3.6 VD1.15
Input voltage (VDD_IO)Vin –0.3 VDD_IO
+ 0.3 VD1.16
Input voltage (
V
DD_MEM_IO
)Vin –0.3
V
DD_MEM_IO
+ 0.3 VD1.17
Input voltage (VBAT_RTC) Vin –0.3 VBAT_RTC
+ 0.3 VD1.18
Input voltage overshoot Vinos — 1 V D1.19
Input voltage undershoot Vinus — 1 V D1.20
Storage temperature range Tstg 55 150 oCD1.21
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 19
3.1.2 Recommended Operating Conditions
Table 5 gives the recommended operating conditions.
3)
Table 5. Recommended Operating Conditions
Characteristic Symbol Min1
1These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Typ Max1Unit SpecID
Supply voltage – e300 core and peripheral
logic VDD_CORE 1.33 1.4 1.47 VD2.1
State Retention voltage – e300 core and
peripheral logic 2
2The State Retention voltage can be applied to VDD_CORE after the device is placed in Deep-Sleep mode.
1.08 — — VD2.2
Supply voltage – standard I / O buffers VDD_IO 3.0 3.3 3.6 VD2.3
Supply voltage – memory I / O buffers (DDR)
V
DD_MEM_IO_DDR
2.3 2.5 2.7 VD2.4
Supply voltage – memory I/O buffers (DDR2,
LPDDR) VDD_MEM_IO_DDR2
V
DD_MEM_IO_LPDDR
1.7 1.8 1.9 VD2.5
Input Reference Voltage (DDR/DDR2) MVREF 0.49 ×
V
DD_MEM_IO
0.50 ×
V
DD_MEM_IO
0.51 ×
V
DD_MEM_IO
VD2.6
Termination Voltage (DDR2) MVTT MVREF
– 0.04 MVREF MVREF
+ 0.04 VD2.7
Supply voltage – System APLL, System
Oscillator SYS_PLL_AVDD 3.0 3.3 3.6 VD2.8
Supply voltage – e300 APLL CORE_PLL_AVDD 3.0 3.3 3.6 VD2.9
Supply voltage – RTC (Hibernation)3
3VBAT_RTC should not be supplied by a battery of voltage less than 3.0 V.
VBAT_RTC 3.0 3.3 3.6 VD2.10
Supply voltage – FUSE Programming AVDD_FUSEWR 3.3 3.6 VD2.11
Supply voltage – SATA PHY analog and OSC SATA_VDDA_3P3 3.0 3.3 3.6 VD2.13
Supply voltage – SATA PHY voltage regulator SATA_VDDA_VREG 1.7 2.6 VD2.14
Supply voltage – SATA PHY Tx/Rx SATA_VDDA_1P2 1.14 1.2 1.47 VD2.15
Supply voltage – SATA PHY PLL
SATA_PLL_VDDA1P2
1.33 1.4 1.47 VD2.16
Supply voltage – USB PHY PLL and OSC USB_PLL_PWR3 3.0 3.3 3.6 VD2.17
Supply voltage – USB PHY transceiver USB_VDDA 3.0 3.3 3.6 VD2.18
Supply voltage – USB PHY bandgap bias USB_VDDA_BIAS 3.0 3.3 3.6 VD2.19
Input voltage – USB PHY cable USB_VBUS 1.4 —3.6 VD2.20
Input voltage – standard I/O buffers Vin 0 — VDD_IO VD2.21
Input voltage – memory I/O buffers (DDR) VinDDR 0—
V
DD_MEM_IO
_DDR
VD2.22
Input voltage – memory I/O buffers (DDR2) VinDDR2 0—VDD_MEM_I
O_DDR2
VD2.23
Input voltage – memory I/O buffers (LPDDR) VinLPDDR 0—VDD_MEM_I
O_LPDR
VD2.24
Ambient operating temperature range TA –40 —+85 oCD2.25
Junction operating temperature range TJ –40 —+125 oCD2.26
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor20
3.1.3 DC Electrical Specifications
Table 6 gives the DC Electrical characteristics for the MPC5121e/MPC5123 at recommended operating conditions.
Table 6. DC Electrical Specifications
Characteristic Condition Symbol Min Max Unit SpecID
Input high voltage Input type = TTL VDD_IO VIH 0.51 × VDD_IO — V D3.1
Input high voltage
Input type = TTL V
DD_MEM_IO_DDR
VIH MVREF + 0.15 — V D3.2
Input high voltage
Input type = TTL
VDD_MEM_IO_DDR2
VIH MVREF + 0.125 — V D3.3
Input high voltage
Input type =
TTL V
DD_MEM_IO_LPDDR
VIH 0.7 ×
V
DD_MEM_IO_LPDDR
— V D3.4
Input high voltage Input type = PCI VDD_IO VIH 0.5 × VDD_IO — V D3.5
Input high voltage Input type = Schmitt VDD_IO VIH 0.65 × VDD_IO — V D3.6
Input high voltage SYS_XTALI crystal mode1
Bypass mode2CVIH Vxtal + 0.4V
(VDD_IO/2) + 0.4V — V D3.7
Input high voltage SATA_XTALI crystal mode
Bypass mode SVIH Vxtal + 0.4V
(VDD_IO/2) + 0.4V — V D3.8
Input high voltage USB_XTALI crystal mode
Bypass mode UVIH Vxtal + 0.4V
(VDD_IO/2) + 0.4V — V D3.9
Input high voltage RTC_XTALI crystal mode3
Bypass mode4
RVIH (VBAT_RTC/5)
+ 0.5V
(VBAT_RTC/2)
+ 0.4V
— V D3.10
Input low voltage Input type = TTL VDD_IO VIL —0.42 × VDD_IO VD3.11
Input low voltage
Input type = TTL V
DD_MEM_IO_DDR
VIL —MVREF – 0.15 VD3.12
Input low voltage
Input type = TTL
VDD_MEM_IO_DDR2
VIL —MVREF – 0.125 VD3.13
Input low voltage Input type =
TTL
V
DD_MEM_IO_LPDDR
VIL —0.3 ×
V
DD_MEM_IO_LPDDR
VD3.14
Input low voltage Input type = PCI VDD_IO VIL —0.3 × VDD_IO VD3.15
Input low voltage Input type = Schmitt VDD_IO VIL —0.35 × VDD_IO VD3.16
Input low voltage SYS_XTALI crystal mode
Bypass mode CVIL —Vxtal – 0.4
(VDD_IO/2) – 0.4 VD3.17
Input low voltage SATA_XTALI crystal mode
Bypass mode SVIL —Vxtal – 0.4 V
(VDD_IO/2) – 0.4 VD3.18
Input low voltage USB_XTALI crystal mode
Bypass mode UVIL —Vxtal – 0.4
(VDD_IO/2) – 0.4 VD3.19
Input low voltage RTC_XTALI crystal mode
Bypass mode RVIL —
(VBAT_RTC/5) – 0.5
(VBAT_RTC/2) – 0.4
VD3.20
Input leakage current Vin = 0 or
VDD_IO/
V
DD_MEM_IO_DDR
/2
(depending on input type)5
IIN 2.5 2.5 µA D3.21
Input leakage current SYS_XTALI Vin = 0 or VDD_IO IIN —20 µA D3.22
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 21
Input leakage current RTC_XTALI Vin = 0 or VDD_IO IIN —1.0 µA D3.23
Input current, pullup
resistor6Pullup VDD_IO Vin = VIL IINpu 25 150 µA D3.24
Input current,
pulldown resistor 8Pulldown VDD_IO Vin = VIH IINpd 25 150 µA D3.25
Output high voltage IOH is driver dependent7 VDD_IO VOH 0.8 × VDD_IO — V D3.26
Output high voltage IOH is driver dependent7
V
DD_MEM_IO_DDR
VOHDDR 1.90 —VD3.27
Output high voltage IOH is driver dependent7
VDD_MEM_IO_DDR2
VOHDDR2 1.396 —VD3.28
Output high voltage IOH is driver dependent7
V
DD_MEM_IO_LPDDR
V
OHLPDDR
V
DD_MEM_IO
– 0.28 — V D3.28
Output low voltage IOL is driver dependent7 VDD_IO VOL —0.2 × VDD_IO VD3.30
Output low voltage IOL is driver dependent7
V
DD_MEM_IO_DDR
VOLDDR —0.36 VD3.31
Output low voltage IOL is driver dependent7
VDD_MEM_IO_DDR2
VOLDDR2 —0.28 VD3.32
Output low voltage IOL is driver dependent7
V
DD_MEM_IO_LPDDR
V
OLLPDDR
—0.28 VD3.33
Differential cross point
voltage
(DDR MCK/MCK)
— VOXMCK
0.5 ×
V
DD_MEM_IO
– 0.125
0.5 ×
V
DD_MEM_IO
+ 0.125
VD3.34
DC Injection Current
Per Pin8— ICS 1.0 1.0 mA D3.35
Input Capacitance
(digital pins) — Cin — 7 pF D3.36
Input Capacitance
(analog pins) — Cin —10 pF D3.37
On Die Termination
(DDR2) — RODT 120 180 D3.38
1This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vextal – Vxtal - 400mV criteria has to be met for oscillator’s comparator to produce output clock.
2This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass
mode. In that case, drive only the EXTAL pin not connecting anything to other pin for the oscillator’s comparator to produce
output clock.
3This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
drive one of the XTAL_IN or XTAL_OUT pins not connecting anything to other pin for the oscillator’s comparator to produce
output clock.
4This parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass
mode. In that case, drive only the xtal_in pin not connecting anything to other pin for the oscillator’s comparator to produce
output clock.
5Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive.
6Pullup current is measured at VIL and pulldown current is measured at VIH.
Table 6. DC Electrical Specifications (continued)
Characteristic Condition Symbol Min Max Unit SpecID
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor22
1
Notes:
1. General IO – Rise and Fall Times at Drive load 50pF.
2. PCI – Rise and Fall Times at Drive load 10pF.
3. DDR – for LPDDR/Mobile-DDR, slew rate is measured between 20% of
V
DD_MEM_IO
and 80% of
V
DD_MEM_IO
.
4. DDR – for DDR, DDR2, rising signals, slew rate is measured between
V
DD_MEM_IO
× 0.5 and ViHAC. For falling signals, slew
rate is measured between
V
DD_MEM_IO
× 0.5 and ViLAC.
5. DDR – Rise and Fall Times terminated at the destination with 50 ohm to MVTT (0.5 ×
V
DD_MEM_IO
), with 4 pF representing the
DDR input capacitance.
7See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin
as listed in Table 3.
8All injection current is transferred to VDD_IO/
V
DD_MEM_IO
. An external load is required to dissipate this current to maintain the
power supply within the specified voltage range.
Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can
cause disruption of normal operation.
Table 7. I/O Pads—Drive Current, Slew Rate
Pad Type Supply Voltage Drive Select/Slew
Rate Control Rise time
max (ns) Fall time
max (ns) Current
Ioh (mA) Current
Iol (mA) SpecID
General IO VDD_IO = 3.3V configuration 3 (11) 1.4 1.6 35 35 D3.41
configuration 2 (10) 9.8 12 D3.42
configuration 1 (01) 19 24 D3.43
configuration 0 (00) 140 183 D3.44
DDR
V
DD_MEM_IO
= 2.5V (DDR)
configuration 3 (011) 2 2 16.2 16.2 D3.45
V
DD_MEM_IO
= 1.8V (LPDDR) configuration 0 (000) 1 1 4.6 4.6 D3.46
configuration 1 (001) 8.1 8.1 D3.47
V
DD_MEM_IO
= 1.8V (DDR2) configuration 2 (010) 1 1 5.3 5.3 D3.48
configuration 6 (110) 13.4 13.4 D3.49
PCI VDD_IO = 3.3V configuration 1 (1) 1.4 1.4 11 17 D3.50
configuration 0 (0) 2 2 D3.51
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 23
3.1.4 Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to high-static voltage or
electrical fields. However, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages. Operational
reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND
or VDD ). Table 10 gives package thermal characteristics for this device.
3.1.5 Power Dissipation
Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core
digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and
CORE_PLL_AVDD), the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the PHYs
(supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of operating
modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each
application case using the following formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f
is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the
device must not exceed the value that would cause the maximum junction temperature to be exceeded.
Eqn. 2
Table 8. ESD and Latch-Up Protection Characteristics
Symbol Rating Min Max Unit SpecID
VHBM Human Body Model (HBM) – JEDEC JESD22-A114-B 2000 — V D4.1
VMM Machine Model (MM) – JEDEC JESD22-A115 200 — V D4.2
VCDM Charge Device Model (CDM) – JEDEC JESD22-C101 500 — V D4.3
Table 9. Power Dissipation
Core Power Supply (VDD_CORE)
SpecID
Mode High-Performance Unit
e300 = 300 MHz, CSB = 200 MHz
Operational1800 mW D5.1
Deep-Sleep11mW D5.2
Hibernation 20 uW D5.3
PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Typical 25 mW D5.4
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO)
PIO PIOint N
M
+CVDD_IO2f=
Ptotal Pcore Panalog PIO PPHYs+++=
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor24
3.1.6 Thermal Characteristics
Typical 300 mW D5.5
PHY Power Supplies (USB_VDDA, SATA_VDDA)
Typical 200 mW D5.6
1Typical core power is measured at VDD_CORE = 1.4 V, Tj = 25 oC.
NOTE
The maximum power depends on the supply voltage, process corner,
junction temperature, and the concrete application and clock
configurations.
The worst case power consumption could reach a maximum of 2000 mW.
Table 10. Thermal Resistance Data
Rating Board Layers Symbol TEPBGA TEPBGA
2Value Unit SpecID
Junction to Ambient Natural
Convection1,2
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Single layer board (1s) RJA 31 24 30 °C/W D6.1
Junction to Ambient Natural
Convection1,3
3Per JEDEC JESD51-6 with the board horizontal.
Four layer board (2s2p) RJMA 22 17 22 °C/W D6.2
Junction to Ambient (@200
ft/min)1,3 Single layer board (1s) RJMA 25 19 24 °C/W D6.3
Junction to Ambient (@200
ft/min)1,3 Four layer board (2s2p) RJMA 19 14 19 °C/W D6.4
Junction to Board4
4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
— RJB 14 914 °C/W D6.5
Junction to Case5
5Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
— RJC 9 7 8 °C/W D6.6
Junction to Package Top6
6Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Natural Convection JT 2 7 2 °C/W D6.7
Table 9. Power Dissipation (continued)
Core Power Supply (VDD_CORE)
SpecID
Mode High-Performance Unit
e300 = 300 MHz, CSB = 200 MHz
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 25
3.1.6.1 Heat Dissipation
An estimation of the chip-junction temperature, TJ, can be obtained from the following equation:
TJ = TA + ( R
JA
PD ) Eqn. 3
where:
TA = ambient temperature for the package ( º C )
R
JA = junction to ambient thermal resistance ( º C / W )
PD = power dissipation in package ( W )
The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board
is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:
R
JA = R
JC + R
CA Eqn. 4
where:
R
JA = junction to ambient thermal resistance ( º C / W )
R
JC = junction to case thermal resistance ( º C / W )
R
CA = case to ambient thermal resistance ( º C / W )
R
JC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient
thermal resistance, R
CA. For instance, you can change the air flow around the device, add a heat sink, change the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This
description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat
sink to ambient. For most packages, a better model is required.
A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal
resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated
from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat
is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics
(CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ = TT + (
JT
PD ) Eqn. 5
where:
TT = thermocouple temperature on top of package ( º C )
JT = thermal characterization parameter ( º C / W )
PD = power dissipation in package ( W )
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor26
from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling
effects of the thermocouple wire.
3.2 Oscillator and PLL Electrical Characteristics
The MPC5121e/MPC5123 System requires a system-level clock input SYS_XTALI. This clock input may be driven directly
from an external oscillator or with a crystal using the internal oscillator.
There is a separate oscillator for the independent Real Time Clock (RTC) system.
The MPC5121e/MPC5123 clock generation uses two phase locked loop (PLL) blocks.
• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The
system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL
configuration.
• The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency
is determined by the system clock frequency and the settings of the CORE_PLL configuration.
The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL.
The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL.
3.2.1 System Oscillator Electrical Characteristics
The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference.
Figure 3. Timing Diagram—SYS_XTALI
Table 11. System Oscillator Electrical Characteristics
Characteristic Symbol Min Typical Max Unit SpecID
SYS_XTALI frequency fsys_xtal 15.6 33.3 35.0 MHz O1.1
Table 12. SYS_XTALI Timing
Sym Description Min Max Units SpecID
t
CYCLE SYS_XTALI cycle time1, 2
1The SYS_XTALI frequency and system PLL settings must be chosen such that the resulting system frequencies do not exceed
their respective maximum or minimum operating frequencies. See the MPC5121e Microcontroller Reference Manual.
2The MIN/Max cycle times are calculated using 1/fsys_xtal (MIN/MAX) where the fsys_xtal (MIN/MAX) (15.6/35 MHz) are taken from
Table 11.
64.1 28.57 ns O.1.2
t
RISE SYS_XTALI rise time3
3Rise time is measured from 20% of vdd to 80% of VDD.
1 4 ns O.1.3
t
FALL SYS_XTALI fall time41 4 ns O.1.4
t
DUTY SYS_XTALI duty cycle5 40 60 %O.1.5
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 27
3.2.2 RTC Oscillator Electrical Characteristics
3.2.3 System PLL Electrical Characteristics
3.2.4 e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled
core PLL.
4Fall time is measured from 20% of vdd to 80% of VDD.
5SYS_XTALI duty cycle is measured at V
M.
Table 13. RTC Oscillator Electrical Characteristics
Characteristic Symbol Min Typical Max Unit SpecID
RTC_XTALI frequency frtc_xtal —32.768 —kHz O2.1
Table 14. System PLL Specifications
Characteristic Symbol Min Typical Max Unit SpecID
Sys PLL input clock frequency1
1The SYS_XTALI frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core)
frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.
fsys_xtal 16 33.3 67 MHz O3.1
Sys PLL input clock jitter2
2This represents total input jitter—short term and long term combined. Two different types of jitter can exist on the input to
CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter is passed into and through the
PLL to the internal clock circuitry.
tjitter — — 10 ps O3.2
Sys PLL VCO frequencyfVCOsys 400 —800 MHz O3.3
Sys PLL VCO output jitter (Dj), peak to peak / cycle fVCOjitterDj — — 40 ps O3.4
Sys PLL VCO output jitter (Rj), RMS 1 sigma fVCOjitterRj — — 12 ps O3.5
Sys PLL relock time—after power up3
3PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached
during the power-on reset sequence.
tlock1 — — 200 sO3.6
Sys PLL relock time—when power was on4
4PLL relock time is the maximum amount of time required for the PLL lock after the PLL has been disabled and subsequently
re-enabled during sleep modes.
tlock2 — — 170 sO3.7
Table 15. e300 PLL Specifications
Characteristic Symbol Min Typical Max Unit SpecID
e300 frequency1fcore 200 —400 MHz O4.1
e300 PLL VCO frequency1fVCOcore 400 —800 MHz O4.3
e300 PLL input clock frequency fCSB_CLK 50 —200 MHz O4.4
e300 PLL input clock cycle time tCSB_CLK 5 — 20 ns O4.5
e300 PLL relock time2tlock — — 200 sO4.6
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor28
1The frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core)
frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in
Table 16. There is a hard coded relationship between fcore and fVCOcore (fcore = fVCOcore/2).
2PLL relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached
during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently
re-enabled during sleep modes.
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 29
3.3 AC Electrical Characteristics
3.3.1 Overview
Hyperlinks to the indicated timing specification sections are provided in the following:
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
•T
A = –40 to 85 oC
•V
DD_CORE = 1.33 to 1.47 V
VDD_IO = 3.0 to 3.6 V
• Input conditions:
All Inputs: tr, tf 1 ns
• Output Loading:
All Outputs: 50 pF
3.3.2 AC Operating Frequency Data
Table 16 provides the operating frequency information for the MPC5121e/MPC5123.
•AC Operating Frequency Data •SDHC
•Resets •DIU
•External Interrupts •SPDIF
•SDRAM (DDR) •CAN
•PCI •I2C
•LPC •J1850
•NFC •PSC
•PATA •GPIOs and Timers
•SATA PHY •Fusebox
•FEC •IEEE 1149.1 (JTAG)
•USB ULPI •VIU
•On-Chip USB PHY
Table 16. Clock Frequencies
Min Max Units SpecID
e300 Processor Core 200 400 MHz A1.1
SDRAM Clock 28.6 200 MHz A1.2
CSB Bus Clock 50.0 200 MHz A1.3
IP Bus Clock 8.3 83 MHz A1.4
PCI Clock 4.43 66 MHz A1.5
LPC Clock 2.08 83 MHz A1.6
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor30
NOTES:
1. The SYS_XTALI frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK,
frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The values are valid for the user operation mode. There can be deviations for test modes.
3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency
limitation.
4.The DDR data rate is 2× the DDR memory bus frequency.
See the MPC5121e Microcontroller Reference Manual for more information on the clock subsystem.
3.3.3 Resets
The MPC5121e/MPC5123 has three reset pins:
•PORESET—Power on Reset
•HRESET—Hard Reset
•SRESET—Software Reset
These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in Section 3.1, “DC Electrical
Characteristics.”
As long as VDD is not stable the HRESET output is not stable.
The timing relationship is shown in Figure 4.
NFC Clock 2.08 83 MHz A1.7
DIU Clock 0.78 100 MHz A1.8
SDHC Clock 0.78 66.6 MHz A1.9
MBX Clock 6.25 100 MHz A1.10
Table 17. Reset Rise / Fall Timing
Description Min Max Unit SpecID
PORESET1 fall time
1Make sure that the PORESET does not carry any glitches. The
MPC5121e/MPC5123 has no filter to prevent them from getting into the chip.
— 1 ms A3.4
PORESET rise time — 1 ms A3.5
HRESET2,3 fall time
2HRESET and SRESET must have a monotonous rise time.
3The assertion of HRESET becomes active at Power on Reset without any
SYS_XTALI clock.
— 1 ms A3.6
HRESET rise time — 1 ms A3.7
SRESET fall time — 1 ms A3.8
SRESET rise time — 1 ms A3.9
Table 16. Clock Frequencies (continued)
Min Max Units SpecID
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 31
Figure 4. Power-Up Behavior
Figure 5. Power-On Reset Behavior
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tHRVAL
tSRVAL
tS_POR_CONF tEXEC
tH_POR_CONF
SYS_XTALI
SYS_XTALI
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tHRVAL
tSRVAL
tS_POR_CONF tEXEC
tH_POR_CONF
tPORHold
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor32
Figure 6. HRESET Behavior
Figure 7. SRESET Behavior
Table 18. Reset Timing
Symbol Description Value
SYS_XTALI SpecID
tPORHOLD Time PORESET must be held low before a qualified reset occurs 4 cycles A3.10
tHRVAL Time HRESET is asserted after a qualified reset occurs 26810 cycles A3.11
tSRVAL Time SRESET is asserted after assertion of HRESET 32 cycles A3.12
tEXEC Time between SRESET assertion and first core instruction fetch 4 cycles A3.13
SYS_XTALI
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tSRVAL
tEXEC
tHRVAL
tHRHOLD
tHR_SR_Delay
no new fetch of the RST_CONF
SYS_XTALI
PORESET
SRESET
HRESET
RST_CONF[31:0]
ADDR[31:0]
tEXEC
tSRMIN
tSRHOLD
no new fetch of the RST_CONF
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 33
3.3.4 External Interrupts
The MPC5121e/MPC5123 provides three different kinds of external interrupts:
• IRQ interrupts
• GPIO interrupts with simple interrupt capability (not available in power-down mode)
• WakeUp interrupts
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.
3.3.5 SDRAM (DDR)
The MPC5121e/MPC5123 memory controller supports three types of DDR devices:
• DDR-1 (SSTL_2 class II interface)
• DDR-2 (SSTL_18 interface)
• LPDDR/Mobile-DDR (1.8V I/O supply voltage)
JEDEC standards define the minimum set of requirements for complient memory devices:
— JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, May 2006
— JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005
— JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006
The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR:
• Full drive strength
• Half drive strengh (intended for ligther loads or point-to-point environments)
The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory
device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical
Characteristics.
tS_POR_CONF Reset configuration setup time before assertion of PORESET 1 cycle A3.14
tH_POR_CONF Reset configuration hold time after assertion of PORESET 1 cycle A3.15
tHR_SR_DELAY Time from falling edge of HRESET to falling edge of SRESET 4 cycles A3.16
tHRHOLD Time HRESET must be held low before a qualified reset occurs 4 cycles A3.17
tSRHOLD Time SRESET must be held low before a qualified reset occurs 4 cycles A3.18
tSRMIN Time SRESET is asserted after it has been qualified 1 cycles A3.19
Table 19. IPIC Input AC Timing Specifications1
1T is the IP bus clock cycle. T = 12 ns is the minimum value (for the maximum IP bus freqency
of 83 MHz).
Description Symbol Min Unit SpecID
IPIC inputs—minimum pulse witdh tPICWID 2T ns A4.1
Table 18. Reset Timing (continued)
Symbol Description Value
SYS_XTALI SpecID
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor34
3.3.5.1 DDR and DDR2 SDRAM AC Timing Specifications
Figure 8 shows the DDR SDRAM write timing.
Figure 8. DDR Write Timing
Figure 9 and Figure 10 shows the DDR SDRAM read timing.
Table 20. DDR and DDR2 (DDR2-400) SDRAM Timing Specifications
At recommended operating conditions with VDD_MEM_IO of 5%
Parameter Symbol Min Max Unit Notes SpecID
Clock cycle time, CL=x tCK 5000 —ps A5.1
CK HIGH pulse width tCH 0.47 0.53 tCK 1,2
1Measured with clock pin loaded with differential 100 termination resistor.
2All transitions measured at mid-supply (VDD_MEM_IO/2).
A5.3
CK LOW pulse width tCL 0.47 0.53 tCK 1,2A5.4
Skew between MCK and DQS
transitions tDQSS 0.25 0.25 tCK 2, 3
3Measured with all outputs except the clock loaded with 50 termination resistor to
V
DD_MEM_IO
/2.
A5.5
Address and control output setup
time relative to MCK rising edge tOS(base) (tCK/2 – 750) —ps 2, 3A5.6
Address and control output hold
time relative to MCK rising edge tOH(base) (tCK/2 – 750) —ps 2, 3A5.7
DQ and DM output setup time
relative to DQS tDS1(base) (tCK/4 – 500) —ps 2, 3A5.8
DQ and DM output hold time relative
to DQS tDH1(base) (tCK/4 – 500) —ps 2, 3A5.9
DQS-DQ skew for DQS and
associated DQ inputs tDQSQ –(tCK/4 – 600) (tCK/4 – 600) ps 2A5.10
DQS window start position related to
CAS read command tDQSEN TBD TBD ps 1,2,3,4,5
4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low.
5Window position is given for tDQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.
A5.11
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 35
Figure 9. DDR Read Timing, DQ vs DQS
Figure 10. DDR Read Timing, DQSEN
Figure 11 provides the AC test load for the DDR bus.
Figure 11. DDR AC Test Load
3.3.6 PCI
The PCI interface on the MPC5121e/MPC5123 is designed to PCI Version 2.3 and supports 33 and 66 MHz PCI operations.
See the PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components
with the intent that components connect directly together whether on the planar or an expansion board, without any external
buffers or other glue logic. Parameters apply at the package pins, not at expansion board edge connectors.
The PCI_CLK is used as output clock, the MPC5121e/MPC5123 is a PCI host device only.
Figure 12 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 21 summarizes
the clock specifications.
Output Z0=50 RL= 50
V
DD_MEM_IO
/2
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor36
Figure 12. PCI CLK Waveform
2Table 21. PCI CLK Specifications
Sym Description 66 MHz1
1In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz. CLK
requirements vary depending upon whether the clock frequency is above 33 MHz.
33 MHz Units SpecID
Min2
2Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 12.
Max Min Max
tcyc PCI CLK Cycle Time1,3
3The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system
jitter.
15 30 30 —ns A6.1
thigh PCI CLK High Time 6 — 11 —ns A6.2
t
low PCI CLK Low Time 6 — 11 —ns A6.3
—PCI CLK Slew Rate21.5 414V/ns A6.4
Table 22. PCI Timing Parameters1
1See the timing measurement conditions in the PCI Local Bus Specification. It is important that all driven
signal transitions drive to their Voh or Vol level within one Tcyc.
Sym Description 66 MHz 33 MHz Units SpecID
Min2
2Minimum times are measured at the package pin with the load circuit, and maximum times are measured
with the load circuit as shown in the PCI Local Bus Specification.
Max Min Max
tval CLK to Signal Valid Delay –
bused signals1,2,3 26211 ns A6.5
tval(ptp) CLK to Signal Valid Delay – point
to point1,2,3 26212 ns A6.6
t
on Float to Active Delay12 — 2 — ns A6.7
t
off Active to Float Delay114 28 ns A6.8
t
su Input Setup Time to CLK – bused
signals3,4 3 — 7 — ns A6.9
t
su(ptp) Input Setup Time to CLK – point
to point3,4
3REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT#
and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.
5 — 10,12 —ns A6.10
t
hInput Hold Time from CLK40 — 0 — ns A6.11
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 37
For Measurement and Test Conditions, see the PCI Local Bus Specification.
3.3.7 LPC
The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects
(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.
The maximum bus frequency is 83 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
HC = Hold Cycle
DS = Data Size in Bytes
BBT = Burst Bytes per Transfer
AL = Address latch enable Length
ALT = Chip select/Address Latch Timing
tLPCck = LPC clock period
4See the timing measurement conditions in the PCI Local Bus Specification.
Table 23. LPC Timing
Sym Description Min Max Units SpecID
tOD CS[x], ADDR, R/W, TSIZ, DATA (wr),
TS, OE valid after LPC CLK
(Output Delay related to LPC CLK)
0 5 ns A7.1
t
1Non-MUXed non-Burst CS[x] pulse
width (2 + WS) × tLPCck (2 + WS) × tLPCck ns A7.2
t
2ADDR, R/W, TSIZ, DATA (wr) valid
before CS[x] assertion tLPCck – tOD tLPCck + tOD ns A7.3
t3OE assertion after CS[x] assertion tLPCck – tOD tLPCck + tOD ns A7.4
t4ADDR, R/W, TSIZ, Data (wr) hold after
CS[x] negation tLPCck – tOD (HC + 1) × tLPCck + tOD ns A7.5
t5TS pulse width tLPCck tLPCck ns A7.6
t6DATA (rd) setup before LPC CLK 4 — ns A7.7
t7DATA (rd) input hold 0 (DC + 1) × tLPCck ns A7.8
t8Non-MUXed read Burst CS[x] pulse
width (2 + WS + BBT/DS) × tLPCck (2 + WS + BBT/DS) × tLPCck ns A7.9
t9Burst ACK pulse width (BBT/DS) × tLPCck (BBT/DS) × tLPCck ns A7.10
t10 Burst DATA (rd) input hold 0 — ns A7.11
t11 Read Burst ACK assertion after CS[x]
assertion (2 + WS) × tLPCck (2 + WS) × tLPCck ns A7.12
t12 Non-muxed write Burst CS[x] pulse
width
(2.5 + WS + BBT/DS) × t
LPCck
(2.5 + WS + BBT/DS) × t
LPCck
ns A7.13
t13 Write Burst ADDR, R/W, TSIZ, DATA
(wr) hold after CS[x] negation 0.5 × tLPCck – tOD (HC + 0.5) × tLPCck + tOD ns A7.14
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor38
t14 Write Burst ACK assertion after CS[x]
assertion (2.5 + WS) × tLPCck – tOD (2.5 + WS) × tLPCck + tOD ns A7.15
t15 Write Burst DATA valid tLPCck – tOD —ns A7.16
t16 Non-MUXed Mode: asynchronous write
Burst ADDR valid before write DATA
valid
0.5 × tLPCck – tOD 0.5 × tLPCck + tOD ns A7.17
t17 MUXed Mode: ADDR cycle AL × 2 × tLPCck – tOD AL × 2 × tLPCck ns A7.18
t18 MUXed Mode: ALE cycle AL × tLPCck AL × tLPCck ns A7.19
t19 Non-MUXed Mode Page Burst: ADDR
cycle tLPCck – tOD tLPCck ns A7.20
t20 Non-MUXed Mode Page Burst: Burst
DATA (rd) input setup before next ADDR
cycle
tOD + t6—ns A7.21
t21 Non-MUXed Mode Page Burst: Burst
DATA (rd) input hold after next ADDR
cycle
0—ns A7.22
t22 MUXed Mode: non-Burst CS[x] pulse
width (ALT × (AL × 2) + 2 + WS)
× tLPCck
(ALT × (AL × 2) + 2 + WS)
× tLPCck
ns A7.23
t23 MUXed Mode: read Burst CS[x] pulse
width [ALT (AL × 2) + 2 + WS
+ BBT/DS] × tLPCck
[ALT × (AL × 2)+2+WS
+BBT/DS] × tLPCck
ns A7.24
t24 MUXed Mode: write Burst CS[x] pulse
width [ALT × (AL × 2) + 2.5 + WS
+ BBT/DS] × tLPCck
[ALT × (AL × 2)+2.5+WS
+BBT/DS] × tLPCck
ns A7.25
Table 23. LPC Timing (continued)
Sym Description Min Max Units SpecID
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 39
3.3.7.1 Non-MUXed Mode
3.3.7.1.1 Non-MUXed Non-Burst Mode
Figure 13. Timing Diagram – Non-MUXed Non-Burst Mode
NOTE
ACK is asynchonous input signal and has no timing requirements. ACK needs to be
deasserted after CS[x] is deasserted.
ADDR
DATA (rd)
CS[x]
R/W
DATA (wr)
OE
t
6
t
7
TS
TSIZ[1:0]
ACK
t
1
LPC CLK
t4
tLPCck
t2t3
t5
L X ‘ g WWW @ HM Q ,,,,,, a D Kg—H \ / ,<—> 4«
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor40
3.3.7.1.2 Non-MUXed Synchronous Read Burst Mode
Figure 14. Timing Diagram – Non-MUXed Synchronous Read Burst Mode
3.3.7.1.3 Non-MUXed Synchronous Write Burst Mode
Figure 15. Timing Diagram – Non-MUXed Synchronous Write Burst
ADDR
DATA (rd)
CS[x]
R/W
OE
TS
ACK
LPC_CLK
Valid Address
t5
t2
t3
t
8
t9
t4
t
6
t
10
t
7
t11
ADDR
CS[x]
R/W
TS
ACK
LPC_CLK
Valid Address
DATA (wr)
t5
t
2
t
13
t
12
t14
t9
t15 t15
\ L \l‘!‘ L 4'7 \l;\\ A
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 41
3.3.7.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode)
Figure 16. Timing Diagram – Non-MUXed Asynchronous Read Burst
3.3.7.1.5 Non-MUXed Aynchronous Write Burst Mode
Figure 17. Timing Diagram – Non-MUXed Aynchronous Write Burst
ADDR[31:n+1]
DATA (rd)
CS[x]
R/W
OE
TS
ACK
LPC_CLK
Valid Address (Page address)
ADDR[n:0] Valid Address Valid Address
t5
t2
t3
t9
t4
t
6
t
10
t
7
t
8
t11
t19
t
20
t
21
ADDR[31:n+1]
CS[x]
R/W
TS
ACK
LPC_CLK
Valid Address (Page address)
ADDR[n:0] Valid Address Valid Address
DATA (wr)
t5
t2
t
13
t
12
t14
t
9
t15 t15
t
16
L
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor42
3.3.7.2 MUXed Mode
3.3.7.2.1 MUXed Non-Burst Mode
Figure 18. Timing Diagram – MUXed Non-Burst Mode
NOTE
ACK is asynchonous input signal and has no timing requirements. ACK needs to be
deasserted after CS[x] is deasserted.
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 43
3.3.7.2.2 MUXed Synchronous Read Burst Mode
Figure 19. Timing Diagram – MUXed Synchronous Read Burst
3.3.7.2.3 MUXed Synchronous Write Burst Mode
Figure 20. Timing Diagram – MUXed Synchronous Write Burst
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor44
3.3.8 NFC
The NAND flash controller (NFC) implements the interface to standard NAND Flash memory devices. This section describes
the timing parameters of the NFC.
Figure 21. Command Latch Cycle Timing
Figure 22. Address Latch Cycle Timing
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 45
Figure 23. Write Data Latch Timing
Figure 24. Read Data Latch Timing
NFC_CLE
NFC_CE[1:0]
NFC_RE
NFC_ALE
NFIO[15:0] Data from NF
tRP
tREA
tREH
tRC
tRHZ
tRR
tAR
R/B
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor46
Figure 25. Read Data Latch Timing in Symmetric Mode
Table 24. NFC Timing Characteristics in asymmetric mode(SYM=0)1
1T is the flash clock cycle.
T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
Timing
parameter Description Min. value Max. value Unit SpecID
tCLS NFC_CLE setup Time T + 1 — ns A8.1
tCLH NFC_CLE Hold Time T – 1 — ns A8.2
tCS NFC_CE[1:0] Setup Time 2T – 1 — ns A8.3
tCH NFC_CE[1:0] Hold Time 3T —ns A8.4
tWP NFC_WP Pulse Width T – 1 — ns A8.5
tALS NFC_ALE Setup Time T – 1 — ns A8.6
tALH NFC_ALE Hold Time T – 1 — ns A8.7
tDS Data Setup Time T – 2 — ns A8.8
tDH Data Hold Time T – 1 — ns A8.9
tWC Write Cycle Time 2T —ns A8.10
tWH NFC_WE Hold Time T – 1 — ns A8.11
tRR Ready to NFC_RE Low 5T + 2 — ns A8.12
tRP NFC_RE Pulse Width 1.5T – 1 — ns A8.13
tRC READ Cycle Time 2T —ns A8.14
tREH NFC_RE High Hold Time 0.5T —ns A8.15
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 47
3.3.9 PATA
The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate
with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is
completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units
( nanoseconds ).
ATA data setup and hold times, with respect to Read / Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5121e Microcontroller Reference Manual.
The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE
strobe in PIO and Multiword DMA modes.
• Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that
required by the ATA-4 specification.
• Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that
required by the ATA-4 specification.
Table 25. NFC Timing Characteristics in Symmetric mode(SYM=1)1
1T is the flash clock cycle.
T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
Timing
Parameter Description Min. value Max. value Unit SpecID
tCLS NFC_CLE Setup time T — ns A8.21
tCLH NFC_CLE Hold time T — ns A8.22
tCS NFC_CE[1:0] Setup time T-2 —ns A8.23
tCH NFC_CE[1:0] Hold time 1.5T-1 —ns A8.24
tWP NFC_WE Pulse width 0.5T+1 —ns A8.25
tALS NFC_ALE Setup time T — ns A8.26
tALH NFC_ALE Hold time T — ns A8.27
tDS Data Setup time 0.5T-3 —ns A8.28
tDH Data Hold time 0.5T —ns A8.29
tWC Write Cycle time T — ns A8.30
tWH NFC_WE Hold time 0.5T-1 —ns A8.31
tRR Ready to NFC_RE low 5T+2 —ns A8.32
tRP NFC_RE pulse width 0.5T —ns A8.33
tRC Read Cycle time T — ns A8.34
tREH NFC_RE High hold time 0.5T —ns A8.35
tSS NFC Read Data setup time 9.6 —ns A8.36
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor48
All ATA transfers are programmed in terms of system clock cycles ( IP bus clocks ) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
Faster ATA modes ( i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate
data transfer rates. Adequate data transfer rates are a function of the following:
• The MPC5121e/MPC5123 operating frequency ( IP bus clock frequency )
• Internal MPC5121e/MPC5123 bus latencies
• Other system load dependent variables
The ATA clock is the same frequency as the IP bus clock in MPC5121e/MPC5123. See the MPC5121e Microcontroller
Reference Manual.
NOTE
All output timing numbers are specified for nominal 50 pF loads.
3.3.9.1 PATA Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface
in silicon, the bus transceiver used, the cable delay and cable skew. The parameters shown in Table 3-26 specify the ATA timing.
Table 3-26. PATA Timing Parameters
Name Meaning Controlled by Value SpecID
TPATA Bus clock period MPC5121E/MPC5123 15 ns A9.1
ti_ds Set-up time ATA_DATA to ATA_IORDY edge (UDMA-in only) MPC5121E/MPC5123 2 ns A9.2
ti_dh Hold time ATA_IORDY edge to ATA_DATA (UDMA-in only) MPC5121E/MPC5123 5 ns A9.3
tco Propagation delay bus clock L-to-H to: ATA_CS0, ATA_CS1, ATA_DA2,
ATA_DA1, ATA_DA0, ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA,
ATA_BUFFER_EN
MPC5121E/MPC5123 2 ns A9.4
tsu Set-up time ATA_DATA to bus clock L-to-H MPC5121E/MPC5123 2 ns A9.5
tsui Set-up time ATA_IORDY to bus clock H-to-L MPC5121E/MPC5123 2 ns A9.6
thi Hold time ATA_IORDY to bus clock H to L MPC5121E/MPC5123 2 ns A9.7
tskew1 Max difference in propagation delay bus clock L-to-H to any of following
signals: ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0,
ATA_DIOR, ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE),
ATA_BUFFER_EN
MPC5121E/MPC5123 1.7 ns A9.8
tskew2 Max difference in buffer propagation delay for any of following signals:
ATA_CS0, ATA_CS1, ATA_DA2, ATA_DA1, ATA_DA0, ATA_DIOR,
ATA_DIOW, ATA_DMACK, ATA_DATA (WRITE), ATA_BUFFER_EN
Transceiver A9.9
tskew3 Max difference in buffer propagation delay for any of following signals:
ATA_IORDY, ATA_DATA (read) Transceiver A9.10
tbuf Max buffer propagation delay Transceiver A9.11
tcable1 Cable propagation delay for ata_data Cable A9.12
tcable2 Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW,
ATA_IORDY, ATA_DMACK Cable A9.13
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 49
3.3.9.2 PIO Mode Timing
A timing diagram for the PIO read mode is given in Figure 26.
Figure 26. PIO Read Mode Timing
To fulfill read mode timing, the different timing parameters given in Table 3-27 must be observed.
tskew4 Max difference in cable propagation delay between: ATA_IORDY and
ATA_DATA (read) Cable A9.14
tskew5 Max difference in cable propagation delay between: ATA_DIOR,
ATA_DIOW, ATA_DMACK and ATA_CS0, ATA_CS1, ATA_DA2,
ATA_DA1, ATA_DA0, ATA_DATA (write)
Cable A9.15
tskew6 Max difference in cable propagation delay without accounting for ground
bounce Cable A9.16
Table 3-27. Timing Parameters PIO Read
ATA
Parameter
PIO Read
Mode Timing
Parameter Value How to meet SpecID
t1t1t1(min) = (time_1 × T) – (tskew1 + tskew2 + tskew5)calculate and programming
time_1. 1 A9.20
t2t2r t2(min) = (time_2r × T) – (tskew1 + tskew2 + tskew5)calculate and programming
time_2r. 1 A9.21
t9t9t9(min) = (time_9 × T) – (tskew1 + tskew2 + tskew6)calculate and programming
time_9. 1 A9.22
Table 3-26. PATA Timing Parameters (continued)
Name Meaning Controlled by Value SpecID
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor50
In PIO write mode, timing waveforms are somewhat different as shown in Figure 27.
Figure 27. PIO Write Mode Timing
To fulfill this timing, several parameters need to be observed as shown in Table 3-28.
t5t5t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 If not met, increase time_2r A9.23
t6t60 — A9.24
tAtAtA(min) = (1.5 + time_ax) × T –
(tco + tsui + tcable2 + tcable2 + 2 × tbuf)calculate and programming
time_ax. 1 A9.25
trd trd1 trd1(max)
= (–
trd
) + (t
skew3
+ t
skew4
)
trd1(min)
= (time_pio_rdx – 0.5 )
×
T – (t
su
+ t
hi
)
(time_pio_rdx – 0.5) × T > t
su
+ t
hi
+ t
skew3
+ t
skew4
calculate and programming
time_pio_rdx. 1 A9.26
t0— t0(min) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9 A9.27
1See the MPC5121e Microcontroller Reference Manual.
Table 3-27. Timing Parameters PIO Read (continued)
ATA
Parameter
PIO Read
Mode Timing
Parameter Value How to meet SpecID
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 51
Table 3-28. Timing Parameters PIO Write
ATA
Parameter
PIO Write
Mode Timing
Parameter Value How to meet SpecID
t1 t1 t1(min) = time_1 × T – (tskew1 + tskew2 + tskew5) time_1. 1
1See the MPC5121e Microcontroller Reference Manual.
A9.30
t2 t2r t2(min) = time_2w × T – (tskew1 + tskew2 + tskew5) calculate and programming
time_2w. 1 A9.31
t9 t9 t9(min) = time_9 × T – (tskew1 + tskew2 + tskew6) time_9. 1 A9.32
t3 —t3(min) = (time_2w – time_on) × T
– (tskew1 + tskew2 + tskew5) If not met, increase time_2w A9.33
t4 t4 t4(min) = time_4 × T – tskew1 calculate and programming
time_4. 1 A9.34
tA tA tA = (1.5 + time_ax) × T
– (tco + tsui + tcable2 + tcable2 + 2 × tbuf) calculate and programming
time_ax. 1 A9.35
t0 —t0(min) = (time_1 + time_2 + time_9) × T time_1, time_2r, time_9 A9.36
— — Avoid bus contention when switching buffer on
by making ton long enough —A9.37
— — Avoid bus contention when switching buffer off
by making toff long enough —A9.38
F F g 4%
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor52
3.3.9.3 Timing in Multiword DMA Mode
Timing in multiword DMA mode is given in Figure 28 and Figure 29.
Figure 28. MDMA Read Timing
Figure 29. MDMA Write Timing
To meet this timing, a number of timing parameters must be controlled as shown in Table 3-29.
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 53
3.3.9.4 UDMA In Timing Diagrams
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in are
given:
•Figure 30 gives timing for UDMA in transfer start
•Figure 31 gives timing for host terminating UDMA in transfer
•Figure 32 gives timing for device terminating UDMA in transfer.
Table 3-29. Timing Parameters MDMA Read and Write
ATA
Parameter
MDMA
Read/Write
Timing
Parameter
Value How to meet SpecID
tm, titm
t
m(min)
= t
i(min)
= (time_m × T) – (t
skew1
+ t
skew2
+ t
skew5
)
calculate and
programming
time_m. 1
1See the MPC5121e Microcontroller Reference Manual.
A9.40
tdtd, td1
t
d1(min)
= t
d(min)
= (time_d × T) – (
t
skew1
+
t
skew2
+
tskew6
)
calculate and
programming
time_d. 1
A9.41
tktktk(min) = (time_k × T) – (
t
skew1 +
t
skew2
+
tskew6
)calculate and
programming
time_k. 1
A9.42
t0— t0(min) = (time_d + time_k) × T time_d, time_k A9.43
tg(read) tgr tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min-drive) = td – te(drive) time_d. 1 A9.44
tf(read) tfr tfr(min-drive) = 0 — A9.45
tg(write) — tg(min-write) = time_d × T – (
t
skew1 +
t
skew2
+
t
skew5
)time_d A9.46
tf(write) — tf(min-write) = time_k × T – (
t
skew1 +
t
skew2
+
tskew6
)time_k A9.47
tL— tL(max) = [(time_d + time_k – 2) × T]
– [tsu + tco + (2 × tbuf) + (2 × tcable2)] time_d, time_k A9.48
tn, tjtkjn tn = tj = tkjn = [max(time_k,. time_jn) × T]
– (
t
skew1 +
t
skew2
+
tskew6
) calculate and
programming
time_jn. 1
A9.49
— ton
toff
ton = (time_on × T) –
t
skew1
toff = (time_off × T) –
t
skew1
—A9.50
{ @# [X
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor54
Figure 30. UDMA In Transfer Start Timing Diagram
XDOCX m W
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 55
Figure 31. UDMA In Host Terminates Transfer
Figure 32. UDMA In Device Terminates Transfer
Timing parameters are explained in Table 30.
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor56
3.3.9.5 UDMA Out Timing Diagrams
UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA out are
given:
•Figure 33 gives timing for UDMA out transfer start
•Figure 34 gives timing for host terminating UDMA out transfer
•Figure 35 gives timing for device terminating UDMA out transfer
Table 30. Timing Parameters UDMA in Burst
ATA
Parameter
UDMA In
Timing
Parameter Value How to Meet SpecID
tack tack tack(min) = (time_ack × T) – (tskew1 + tskew2)
calculate and
programming time_ack.
1
1See the MPC5121e Microcontroller Reference Manual.
A9.51
tenv tenv tenv(min) = (time_env × T) – (tskew1 + tskew2)
tenv(max) = (time_env × T) + (tskew1 + tskew2)
calculate and
programming time_env.
1
A9.52
tds tds1 tds – (tskew3) – ti_ds > 0 tskew3, ti_ds, ti_dh should
be low enough A9.53
tdh tdh1 tdh – (tskew3) – ti_dh > 0 A9.54
tcyc tc1 (tcyc – tskew ) > T Bus clock period T big
enough A9.55
trp trp trp(min) = time_rp × T – (tskew1 + tskew2 + tskew6)calculate and
programming time_rp
.
1
A9.56
—tx12
2A special timing requirement in the ATA host requires the internal DIOW to go only high three clocks after the last active edge
on the DSTROBE signal. The equation given on this line tries to capture this constraint.
(time_rp × T) –
[tco + tsu + 3T + (2 × t
buf
) + (2 × tcable2)]
>
trfs (drive) calculate and
programming time_rp
.
1
A9.57
tmli tmli1 tmli1(min) = (time_mlix + 0.4) × T
calculate and
programming time_mlix.
1
A9.58
tzah tzah tzah(min) = (time_zah + 0.4) × T
calculate and
programming time_zah.
1
A9.59
tdzfs tdzfs tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
calculate and
programming time_dzfs.
1
A9.60
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2)
calculate and
programming time_cvh.
1
A9.61
—ton
toff3
3Make ton and toff large enough to avoid bus contention.
ton = (time_on × T) – tskew1
toff = (time_off × T) – tskew1 —A9.62
env ‘cyc on dzls luvs ‘dvm tavs r151 um um cvh an ha
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 57
Figure 33. UDMA Out Transfer Start Timing Diagram
Figure 34. UDMA Out Host Terminates Transfer
—/ c c dzts mh am an
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor58
r
Figure 35. UDMA Out Device Terminates Transfer
Timing parameters are explained in Table 31.
Table 31. Timing Parameters UDMA Out Burst
ATA
Parameter
UDMA Out
Timing
Parameter Value How to meet SpecID
tack tack tack(min) = (time_ack × T) – (tskew1 + tskew2)calculate and program
time_ack.
1
A9.63
tenv tenv tenv(min) = (time_env × T) – (tskew1 + tskew2)
tenv(max) = (time_env × T) + (tskew1 + tskew2)calculate and program
time_env
.
1
A9.64
tdvs tdvs tdvs = (time_dvs × T) – (tskew1 + tskew2)calculate and program
time_dvs
.
1
A9.65
tdvh tdvh tdvs = (time_dvh × T) – (tskew1 + tskew2)calculate and program
time_dvh
.
1
A9.66
tcyc tcyc tcyc = time_cyc × T – (tskew1 + tskew2)calculate and program
time_cyc
.
1
A9.67
t2cyc —t2cyc = time_cyc × 2 × T calculate and program
time_cyc
.
1
A9.68
trfs1 trfs1 trfs1 = 1.6 × T + tsui + tco + tbuf + tbuf —A9.69
—tdzfs tdzfs = time_dzfs × T – (tskew1)calculate and program
time_dzfs
.
1
A9.70
tss tss tss = time_ss × T – (tskew1 + tskew2)
calculate and program
time_ss.
1
A9.71
tmli tdzfs_mli tdzfs_mli = max(time_dzfs, time_mli) × T –
(tskew1 + tskew2)—A9.72
tli tli1 tli1 > 0 — A9.73
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 59
3.3.10 SATA PHY
1.5 Gbps SATA PHY Layer
See “Serial ATA: High Speed Serialized AT Attachment” Revision 1.0a, 7-January-2003.
3.3.11 FEC
AC Test Timing Conditions:
• Output Loading
All Outputs: 25 pF
Figure 36. Ethernet Timing Diagram – MII Rx Signal
tli tli2 tli2 > 0 — A9.74
tli tli3 tli3 > 0 — A9.75
tcvh tcvh tcvh = (time_cvh × T) – (tskew1 + tskew2)calculate and program
time_cvh
.
1
A9.76
—ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
—A9.77
1See the MPC5121e Microcontroller Reference Manual.
Table 32. MII Rx Signal Timing
Symbol Description Min Max Unit SpecID
1RXD [ 3 : 0 ], RX_DV, RX_ER to RX_CLK setup 5 — ns A11.1
2RX_CLK to RXD [ 3 : 0 ], RX_DV, RX_ER hold 5 — ns A11.2
3RX_CLK pulse width high 35% 65% RX_CLK Period1
1RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification.
A11.3
4RX_CLK pulse width low 35% 65% RX_CLK Period1A11.4
Table 31. Timing Parameters UDMA Out Burst (continued)
ATA
Parameter
UDMA Out
Timing
Parameter Value How to meet SpecID
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor60
Figure 37. Ethernet Timing Diagram – MII Tx Signal
Figure 38. Ethernet Timing Diagram – MII Async
Table 33. MII Tx Signal Timing
Symbol Description Min Max Unit SpecID
5TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER
invalid 3 — ns A11.5
6TX_CLK rising edge to TXD [ 3 : 0 ], TX_EN, TX_ER valid —25 ns A11.6
7TX_CLK pulse width high 35% 65% TX_CLK Period1
1The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
A11.7
8TX_CLK pulse width low 35% 65% TX_CLK Period1A11.8
Table 34. MII Async Signal Timing
Symbol Description Min Max Unit SpecID
9CRS, COL minimum pulse width 1.5 — TX_CLK Period A11.9
Table 35. MII Serial Management Channel Signal Timing
Symbol Description Min Max Unit SpecID
10 MDC falling edge to MDIO output delay 025 ns A11.10
11 MDIO ( input ) to MDC rising edge setup 10 —ns A11.11
12 MDIO ( input ) to MDC rising edge hold 0 — ns A11.12
13 MDC pulse width high1
1MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC
MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.
160 —ns A11.13
14 MDC pulse width low1160 —ns A11.14
15 MDC period2400 —ns A11.15
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 61
Figure 39. Ethernet Timing Diagram – MII Serial Management
2The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference
Manual.
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor62
3.3.12 USB ULPI
This section specifies the USB ULPI timing.
For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004.
Figure 40. ULPI Timing Diagram
NOTE
Output timing is specified at a nominal 50 pF load.
3.3.13 On-Chip USB PHY
The USB PHY is an USB2.0 compatible PHY integrated on-chip. See Chapter 7 in the USB Specification Rev. 2.0 at
www.usb.org.
3.3.14 SDHC
Figure 41 shows the timings of the SDHC.
Table 36. Timing Specifications – ULPI
Symbol Description Min Max Units SpecID
TCK Clock Period 15 —ns A12.1
TSC, TSD Setup time (control in, 8-bit data in) —6.0 ns A12.2
THC, THD Hold time (control in, 8-bit data in) 0.0 —ns A12.3
TDC, TDD Output delay (control out, 8-bit data out) —9.0 ns A12.4
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 63
Figure 41. SDHC Timing Diagram
Table 37 lists the timing parameters.
.Table 37. MMC/SD Interface Timing Parameters
ID Parameter Symbols Min Max Unit SpecID
Card Input Clock
SD1 Clock Frequency (Low Speed) fPP1
1In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
0400 kHz A14.1
Clock Frequency (SD/SDIO Full
Speed/High Speed) fPP2
2In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz.
025/50 MHz A14.2
Clock Frequency (MMC Full Speed/High
Speed) fPP3
3In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz.
020/52 MHz A14.3
Clock Frequency (Identification Mode) fOD4
4In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.
100 400 kHz A14.4
SD2 Clock Low Time (Full Speed/High Speed) tWL 10/7 ns A14.5
SD3 Clock High Time (Full Speed/High Speed) tWH 10/7 ns A14.6
SD4 Clock Rise Time (Full Speed/High Speed) tTLH 10/3 ns A14.7
SD5 Clock Fall Time (Full Speed/High Speed) tTHL 10/3 ns A14.8
SDHC Output / Card Inputs CMD, DAT (Reference to CLK)
SD6 SDHC Output Delay tOD TH5 – 3
5Suggested ClockPeriod = T, CLK_DIVIDER (in SDHC Clock Rate Register) = D, then TH = [(D + 1)/2]/(D + 1) × T
where the value is rounded.
TH+3 ns A14.9
SDHC Input / Card Outputs CMD, DAT (Reference to CLK)
SD7 SDHC Input Setup Time tISU 2.5 ns A14.10
SD8 SDHC Input Hold Time tIH 2.5 ns A14.11
j m [MW ,,,,,,,,,,,,,,,, U_L DIUiHSVNC DIUiDE m K; muicm r 1 I 1 I 1 I 1 I 1 I 1 m DIU,LD[23:0] XXXXX:X:X:X:)C : 3C : :X:X:)C : X : )<:xxxxx>
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor64
3.3.15 DIU
The DIU is a display controller designed to manage the TFT LCD display.
3.3.15.1 Interface to TFT LCD Panels, Functional Description
Figure 42 shows the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with
positive polarity. The sequence of events for active matrix interface timing is:
• DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode,
DIU_CLK runs continuously. This signal frequency could be from 5 to 100 MHz depending on the panel type.
• DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.
• DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.
• DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
Figure 42. Interface Timing Diagram for TFT LCD Panels
3.3.15.2 Interface to TFT LCD Panels, Electrical Characteristics
Figure 43 shows the horizontal timing (timing of one line), including the horizontal sync pulse and the data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK signal
(meaning the data and sync. signals change at the rising edge of it) and active-high polarity of the DIU_HSYNC, DIU_VSYNC
and DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register,
whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock
inversion and a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register
(DCCR) in the system clock module.
\HJ \HW
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 65
Figure 43. TFT LCD Interface Timing Diagram – Horizontal Sync Pulse
Figure 44 shows the vertical timing (timing of one frame), including the vertical sync pulse and the data. All parameters shown
in the diagram are programmable.
Figure 44. TFT LCD Interface Timing Diagram – Vertical Sync Pulse
Table 38 shows timing parameters of signals.
Table 38. LCD Interface Timing Parameters – Pixel Level
Name Description Value Unit SpecID
tPCP Display Pixel Clock Period 151ns A15.1
tPWH HSYNC Pulse Width PW_H × tPCP ns A15.2
tBPH HSYNC Back Porch Width BP_H × tPCP ns A15.3
LL
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor66
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H
parameters are programmed via the HSYN_PARA register; And the PW_V, BP_V and FP_V parameters are programmed via
the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions on these parameters.
Figure 45 shows the synchronous display interface timing for access level, and Table 39 lists the timing parameters.
Figure 45. LCD Interface Timing Diagram – Access Level
tFPH HSYNC Front Porch Width FP_H × tPCP ns A15.4
tSW Screen Width DELTA_X × tPCP ns A15.5
tHSP HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H) × tPCP ns A15.6
tPWV VSYNC Pulse Width PW_V × tHSP ns A15.7
tBPV VSYNC Back Porch Width BP_V × tHSP ns A15.8
tFPV VSYNC Front Porch Width FP_V × tHSP ns A15.9
tSH Screen Height DELTA_Y × tHSP ns A15.10
tVSP VSYNC (Frame) Period (PW_V + BP_V + DELTA_Y + FP_H) × tHSP ns A15.11
1 Display interface pixel clock period immediate value (in nanosecond).
Table 39. LCD Interface Timing Parameters – Access Level
Parameter Description Min Typ Max Unit SpecID
tCKH LCD Interface Pixel Clock High Time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.12
tCKL LCD Interface Pixel Clock Low Time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.13
tDSU LCD Interface Data Setup Time 5.0 — — ns A15.14
tDHD LCD Interface Data Hold Time 6.0 — — ns A15.15
tCSU LCD Interface Control Signal Setup Time 5.0 — — ns A15.16
tCHD LCD Interface Control Signal Hold Time 6.0 — — ns A15.17
Table 38. LCD Interface Timing Parameters – Pixel Level (continued)
Name Description Value Unit SpecID
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 67
3.3.16 SPDIF
The Sony/Philips Digital Interface (SPDIF) timing is totally asynchronous, therefore there is no need for relationship with the
clock.
3.3.17 CAN
The CAN functions are available as TX and CAN3/4_RX pins at normal IO pads and as CAN1/2 RX pins at the VBAT_RTC
domain. There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
3.3.18 I2C
This section specifies the timing parameters of the Inter-Integrated Circuit (I2C) interface. Refer to the I2C Bus Specification.
Table 40. I2C Input Timing Specifications – SCL and SDA
Symbol Description Min Max Units SpecID
1 Start condition hold time 2 — IP-Bus Cycle1
1Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.
A18.1
2 Clock low time 8 — IP-Bus Cycle1A18.2
4 Data hold time 0.0 —ns A18.3
6 Clock high time 4 — IP-Bus Cycle1A18.4
7 Data setup time 0.0 —ns A18.5
8
Start condition setup time ( for repeated start condition only )
2 — IP-Bus Cycle1A18.6
9 Stop condition setup time 2 — IP-Bus Cycle1A18.7
Table 41. I2C Output Timing Specifications – SCL and SDA
Symbol Description Min Max Units SpecID
1
1
1Programming IFDR with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to
scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and
division values programmed in IFDR.
Start condition hold time 6 — IP-Bus Cycle2
2Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA
takes to reach a high level depends on external signal capacitance and pull-up resistor values.
A18.8
2 1Clock low time 10 —IP-Bus Cycle2A18.9
33
3Inter Peripheral Clock is defined in the MPC5121e/MPC5123 Reference Manual.
SCL / SDA rise time —7.9 ns A18.10
41Data hold time 7 — IP-Bus Cycle2A18.11
51SCL / SDA fall time —7.9 ns A18.12
61Clock high time 10 —IP-Bus Cycle2A18.13
71Data setup time 2 — IP-Bus Cycle2A18.14
81
Start condition setup time ( for repeated start condition only )
20 —IP-Bus Cycle2A18.15
91Stop condition setup time 10 —IP-Bus Cycle2A18.16
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor68
NOTE
Output timing is specified at a nominal 50 pF load.
Figure 46. Timing Diagram – I2C Input / Output
3.3.19 J1850
See the MPC5121e/MPC5123 Reference Manual.
3.3.20 PSC
The Programmable Serial Controllers (PSC) support different modes of operation (UART, Codec, AC97, SPI). UART is an
asynchronous interface, there is no AC characteristic.
3.3.20.1 Codec Mode (8,16,24 and 32-bit)/I2S Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 42. Timing Specifications – 8,16, 24, and 32-bit CODEC/I2S Master Mode
Symbol Description Min Typ Max Units SpecID
1 Bit Clock cycle time, programmed in CCS register 40.0 — — ns A20.1
2 Clock duty cycle 45 50 55 %1
1Bit Clock cycle time
A20.2
3 Bit Clock fall time — — 7.9 ns A20.3
4 Bit Clock rise time — — 7.9 ns A20.4
5 FrameSync valid after clock edge — — 8.4 ns A20.5
6 FrameSync invalid after clock edge — — 8.4 ns A20.6
7 Output Data valid after clock edge — — 9.3 ns A20.7
8 Input Data setup time 6.0 — — ns A20.8
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 69
Figure 47. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I2S Master Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 43. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I2S Slave Mode
Symbol Description Min Typ Max Units SpecID
1 Bit Clock cycle time 40.0 — — ns A20.9
2 Clock duty cycle —50 — %1
1Bit Clock cycle time
A20.10
3 FrameSync setup time 1.0 — — ns A20.11
4 Output Data valid after clock edge — — 14.0 ns A20.12
5 Input Data setup time 1.0 — — ns A20.13
6Input Data hold time 1.0 — — ns A20.14
$6)
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor70
Figure 48. Timing Diagram – 8,16, 24, and 32-bit CODEC/I2S Slave Mode
3.3.20.2 AC97 Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 44. Timing Specifications – AC97 Mode
Symbol Description Min Typ Max Units SpecID
1 Bit Clock cycle time —81.4 —ns A20.15
2 Clock pulse high time —40.7 —ns A20.16
3 Clock pulse low time —40.7 —ns A20.17
4 FrameSync valid after rising clock edge — — 13.0 ns A20.18
5 Output Data valid after rising clock edge — — 14.0 ns A20.19
6Input Data setup time 1.0 — — ns A20.20
7Input Data hold time 1.0 — — ns A20.21
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 71
Figure 49. Timing Diagram – AC97 Mode
3.3.20.3 SPI Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 45. Timing Specifications – SPI Master Mode, Format 0 (CPHA = 0)
Symbol Description Min Max Units SpecID
1SCK cycle time, programable in the PSC CCS register 30.0 —ns A20.26
2SCK pulse width, 50% SCK duty cycle 15.0 —ns A20.27
3Slave select clock delay, programable in the PSC CCS register 30.0 —ns A20.28
4 Output Data valid after Slave Select (SS) — 8.9 ns A20.29
5Output Data valid after SCK —8.9 ns A20.30
6Input Data setup time 6.0 —ns A20.31
7Input Data hold time 1.0 —ns A20.32
8Slave disable lag time —TSCK ns A20.33
9Sequential Transfer delay, programmable in the PSC CTUR / CTLR register 15.0 —ns A20.34
10 Clock falling time —7.9 ns A20.35
11 Clock rising time —7.9 ns A20.36
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor72
Figure 50. Timing Diagram – SPI Master Mode, Format 0 (CPHA = 0)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 46. Timing Specifications – SPI Slave Mode, Format 0 (CPHA = 0)
Symbol Description Min Max Units SpecID
1SCK cycle time, programable in the PSC CCS register 30.0 —ns A20.37
2SCK pulse width, 50% SCK duty cycle 15.0 —ns A20.38
3Slave select clock delay 1.0 —ns A20.39
4Input Data setup time 1.0 —ns A20.40
5Input Data hold time 1.0 —ns A20.41
6Output data valid after SS —14.0 ns A20.42
7Output data valid after SCK —14.0 ns A20.43
8Slave disable lag time 0.0 —ns A20.44
9Minimum Sequential Transfer delay = 2 × IP Bus clock cycle time 30.0 — — A20.45
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 73
Figure 51. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 47. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1)
Symbol Description Min Max Units SpecID
1SCK cycle time, programable in the PSC CCS register 30.0 —ns A20.46
2SCK pulse width, 50% SCK duty cycle 15.0 —ns A20.47
3Slave select clock delay, programable in the PSC CCS register 30.0 —ns A20.48
4Output data valid —8.9 ns A20.49
5Input Data setup time 6.0 —ns A20.50
6Input Data hold time 1.0 —ns A20.51
7Slave disable lag time —TSCK ns A20.52
8
Sequential Transfer delay, programable in the PSC CTUR / CTLR register
15.0 —ns A20.53
9Clock falling time —7.9 ns A20.54
10 Clock rising time —7.9 ns A20.55
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor74
Figure 52. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 48. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1)
Symbol Description Min Max Units SpecID
1SCK cycle time, programable in the PSC CCS register 30.0 —ns A20.56
2SCK pulse width, 50% SCK duty cycle 15.0 —ns A20.57
3Slave select clock delay 0.0 —ns A20.58
4Output data valid —14.0 ns A20.59
5Input Data setup time 2.0 —ns A20.60
6Input Data hold time 1.0 —ns A20.61
7Slave disable lag time 0.0 —ns A20.62
8Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time 30.0 —ns A20.63
(( (( (( x u *1:sz—
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 75
Figure 53. Timing Diagram – SPI Slave Mode, Format 1 (CPHA = 1)
3.3.21 GPIOs and Timers
The MPC5121e/MPC5123 contains several sets of I/Os that do not require special setup, hold, or valid requirements. The
external events (GPIO or timer inputs) are asynchronous to the system clock. The inputs must be valid for at least tIOWID to
ensure proper capture by the internal IP clock.
3.3.22 Fusebox
Table 50 gives the Fusebox specification.
Table 49. GPIO/Timers Input AC Timing Specifications
Symbol Description Min Unit SpecID
tIOWID GPIO/Timers inputs—minimum pulse width 2T1
1T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus frequency of 83 MHz).
ns A21.1
Table 50. Fusebox Characteristics
Symbol Description Min Max Units SpecID
tFUSEWR Program time1 for Fuse
1The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module.
125 —us A22.1
IFUSEWR Program current to program one fuse bit —10 mA A22.2
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor76
3.3.23 IEEE 1149.1 (JTAG)
Figure 54. Timing Diagram – JTAG Clock Input
Table 51. JTAG Timing Specification
Symbol Characteristic Min Max Unit SpecID
—TCK frequency of operation 025 MHz A23.1
1TCK cycle time 40 —ns A23.2
2TCK clock pulse width measured at 1.5 V 1.08 —ns A23.3
3TCK rise and fall times 0 3 ns A23.4
4TRST setup time to tck falling edge1
1TRST is an asynchronous signal. The setup time is for test purposes only.
10 —ns A23.5
5TRST assert time 5 — ns A23.6
6Input data setup time2
2Non-test, other than TDI and TMS, signal input timing with respect to TCK.
5 — ns A23.7
7Input data hold time15 —ns A23.8
8TCK to output data valid3
3Non-test, other than TDO, signal output timing with respect to TCK.
030 ns A23.9
9TCK to output high impedance3030 ns A23.10
10 TMS, TDI data setup time. 5 — ns A23.11
11 TMS, TDI data hold time. 1 — ns A23.12
12 TCK to TDO data valid. 015 ns A23.13
13 TCK to TDO high impedance. 015 ns A23.14
® @ ® N0 NN® NN®
Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 77
Figure 55. Timing Diagram – JTAG TRST
Figure 56. Timing Diagram – JTAG Boundary Scan
Figure 57. Timing Diagram – Test Access Port
LP fl
MPC5121E/MPC5123 Data Sheet, Rev. 5
Electrical and Thermal Characteristics
Freescale Semiconductor78
3.3.24 VIU
The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream.
Figure 58 shows the VIU interface timing and Table 52 lists the timing parameters.
Figure 58. VIU Interface Timing Diagram
Table 52. VIU Interface Timing Parameters
Parameter Description Min Typ Max Unit SpecID
fPIX_CK VIU Pixel Clock Frequency — — 83 MHz A24.1
tDSU VIU Data Setup Time 2.5 — — ns A24.2
tDHD VIU Data Hold Time 2.5 — — ns A24.3
System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 79
4 System Design Information
4.1 Power Up/Down Sequencing
Power sequencing between the 1.4 V power supply VDD_CORE and the remaining supplies is required to prevent excessive
current during power up phase.
The required power sequence is as follows:
•Use 12 V/millisecond or slower time for all supplies.
• Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, USB PHY, and SATA PHY
supplies first in any order and then power up VDD_CORE. If required, AVDD_FUSEWR should be powered up afterwards.
• All the supplies must reach the specified operating conditions before the PORESET can be released.
• For power down, drop AVDD_FUSEWR to 0 V first, drop VDD_CORE to 0 V, and then drop all other supplies.
•V
DD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC, or PLL_AVDDs by more than 0.4 V at any time,
including power-up.
4.2 System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 59 is a
recommendation for the required filter circuit.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
The filter for System/Core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the
planes.
In addition to keeping the filter components for System/Core PLLVDD as close as practical to the body of the MPC5121e as
previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise
onto the portion of that supply between the filter and the MPC5121e.
Figure 59. Power Supply Filtering
The capacitors for C2 in Figure 59 should be rated X5R or better due to temperature performance. It is recommended to add a
bypass capacitance of at least 1 µF for the VBAT_RTC pin.
4.3 Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to
VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD and VSS pins of the MPC5121e/MPC5123.
The unused AVDD_FUSEWR power should be connected to VSS directly or via a resistor.
For DDR or LPDDR modes the unused pins MVTT[3:0] for DDR2 Termination voltage can be unconnected.
MPC5121E/MPC5123 Data Sheet, Rev. 5
System Design Information
Freescale Semiconductor80
The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA
oscillator and the SATA PHY by software.
Figure 60. Recommended Connection for Pins of Unused SATA PHY
Figure 61. Recommended connection for pins of unused USB PHY
4.4 Pull-Up/Pull-Down Resistor Requirements
The MPC5121e/MPC5123 requires external pull-up or pull-down resistors on certain pins.
4.4.1 Pull-Down Resistor Requirements for TEST pin
The MPC5121e/MPC5123 requires a pull-down resistor on the test pin TEST.
System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 81
4.4.2 Pull-Up Requirements for the PCI Control Lines
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
Refer to the PCI Local Bus specification.
4.5 JTAG
The MPC5121e/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides
a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port.
The COP Interface provides access to the MPC5121e/MPC5123’s embedded e300 processor and to other on-chip resources.
This interface provides a means for executing test routines and for performing software development and debug functions.
4.5.1 TRST
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the Power Architecture. To obtain a reliable power-on reset
performance, the TRST signal must be asserted during power-on reset.
4.5.1.1 TRST and PORESET
The JTAG interface can control the direction of the MPC5121e/MPC5123 I/O pads via the boundary scan chain. The JTAG
module must be reset before the MPC5121e/MPC5123 comes out of power-on reset; do this by asserting TRST before
PORESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 62. PORESET vs. TRST
4.5.2 e300 COP / BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
4.5.2.1 Boards Interfacing the JTAG Port via a COP Connector
The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core
through the Freescale standard COP / BDM interface. Table 53 gives the COP / BDM interface signals. The pin order shown
reflects only the COP / BDM connector order.
MPC5121E/MPC5123 Data Sheet, Rev. 5
System Design Information
Freescale Semiconductor82
For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG
module, only wiring TRST and PORESET is not recommended.
To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET
pin of the MPC5121e/MPC5123. The circuitry shown in Figure 63 allows the COP to assert HRESET or TRST separately,
while any other board sources can drive PORESET.
Table 53. COP / BDM Interface Signals
BDM Pin # MPC5121e/MPC5123 I / O Pin BDM Connector Internal
Pull Up / Down External
Pull Up / Down I / O
1
1With respect to the emulator tool’s perspective:
Input is really an output from the embedded e300 core.
Output is really an input to the core.
16 — GND — — —
15 CKSTP_OUT ckstp_out —10 k Pull-up I
14 —KEY — — —
13 HRESET hreset Pull-up 10 k Pull-up O
12 — GND — — —
11 SRESET sreset Pull-up 10 k Pull-up O
10 — N / C — — —
9TMS tms Pull-up 10 k Pull-up O
8CKSTP_IN ckstp_in —10 k Pull-up O
7TCK tck Pull-up 10 k Pull-up O
6 — VDD
2
2From the board under test, power sense for chip power.
— — —
5See Note3
3HALTED is not available from e300 core.
halted3— — I
4TRST trst Pull-up 10 k Pull-up O
3TDI tdi Pull-up 10 k Pull-up O
2See Note4
4Input to the e300 core to enable / disable soft-stop condition during breakpoints. MPC5121e/MPC5123
internally ties CORE_QACK to GND in its normal / functional mode (always asserted).
qack4— — O
1TDO tdo — — I
DE DE DE DE DE DE DE DE W H m “H L TDI w fl
System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 83
Figure 63. COP Connector Diagram
4.5.2.2 Boards Without COP Connector
If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal
(PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 64 shows the connection
of the JTAG interface without COP connector.
P? $HESET 7 10k!)
MPC5121E/MPC5123 Data Sheet, Rev. 5
System Design Information
Freescale Semiconductor84
Figure 64. TRST Wiring for Boards without COP Connector
Package Information
MPC5121E/MPC5123 Data Sheet, Rev. 5
Freescale Semiconductor 85
5 Package Information
This section details package parameters and dimensions. The MPC5121e/MPC5123 is available in a Thermally Enhanced
Plastic Ball Grid Array (TEPBGA), see Section 5.1, “Package Parameters,” and Section 5.2, “Mechanical Dimensions,” for
information on the TEPBGA.
5.1 Package Parameters
5.2 Mechanical Dimensions
Figure 65 shows the mechanical dimensions and bottom surface nomenclature of the MPC5121e/MPC5123 516 PBGA
package.
Table 54. TEPBGA Parameters
Package outline 27 mm 27 mm
Interconnects 516
Pitch 1.00 mm
Module height (typical) 2.25 mm
Solder Balls 96.5 Sn/3.5Ag (VY package)
Ball diameter (typical) 0.6 mm
Al mozx E {E SEATING FLAME 2&3 —\ 23,7 (3 fl 131 ll] TOP VIEW 25X 1 nus-11mm: msununnnnunau IX X X 1 L ~1~ 3 I T 51“ u ’ v 9 l ‘ 5 E05 ‘ .x > , 1 E; > g ’ i (25) 1 it , g x '6 x : fig; * ’ if? raga 1 E 0.5 V! X x X 8_§_ ' 0.7 . 25x 1 —--|I——|fi| 5‘“ ’o.5 2‘55 fl 0.25 A B C 1.95 (25) 9 ¢ map A ' SIDE vuzw BOTTOM VIEW
MPC5121E/MPC5123 Data Sheet, Rev. 5
Package Information
Freescale Semiconductor86
Figure 65. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121e/MPC5123 TEPBGA
1All dimensions are in millimeters.
2Dimensions and tolerances per ASME Y14.5M-1994.
3Maximum solder ball diameter measured parallel to datum A.
4Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC5121E/MPC5123 Data Sheet, Rev. 5
Product Documentation
Freescale Semiconductor87
6 Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.freescale.com.
Table 55 provides a revision history for this document.
Table 55. Document Revision History
Revision Substantive Change(s)
Rev. 0, DraftA First Draft (5/2008)
Rev. 0, DraftB Second Draft (5/2008)
Rev. 0, DraftC Third Draft (7/2008)
Rev. 1 Advance Information (10/2008)
Rev. 2 Technical Data (2/2009)
Rev. 3 Technical Data (2/2009). Corrected Table 5, Footnote 3.
Rev. 3.1 Technical Data (12/2009). Interim release for removing AVDD_FUSERD
throughout document, changing pin D9 to VDD_IO, and adding D9 to list of
pins for VDD_IO.
Rev. 4 Technical Data (1/2010). Minor editorial and graphical updates.
No technical updates.
Rev 5 — Updated table “DDR and DDR2 SDRAM Timing Specification”, removed
the row of ‘MCK AC differential crosspoint voltage' .
— Updated table “Thermal Resistance Data”.
— Added table “NFC Timing Characteristics in Symmetric Mode ”and
added figure “Read data latch timing in Symmetric Mode”.
—Published as Rev. 5
oo' :" freescalew semiconductor
Document Number: MPC5121E
Rev. 5
02/2012
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