Continuing on with NOR Flash Memory terms, the first term to look at is HyperBus. This is a Cypress developed, high bandwidth, 12 signal interface which transfers information over 8 I/O signals and DDR, and can deliver up to 333 megabytes per second (MBps). The figure shown here on the right actually displays the interface and the 12 mandatory pins which are required for data transactions. First there are the 8 I/O signals, a chip select, a differential clock pair, and a Read Write Data Strobe. One other thing about the HyperBus is that although in this PTM memory with the HyperBus will be discussed, the HyperBus could also support other types of I/O peripherals as well. The first product to be released with the HyperBus interface is HyperFlash. HyperFlash is a Cypress NOR Flash memory product which offers higher bandwidth and Quad SPI, with 1/3 the number of pins as parallel NOR Flash memory. One thing that will be discussed throughout this whole presentation is that HyperFlash can be compared with the Quad SPI because they are very similar in interfaces; however, it is important to note that HyperFlash and SPI have completely different command sets so they are not compatible in that sense. Serial peripheral interface (SPI) is an industry standard, low pin count interface which enables synchronous data transactions between a master and slave device that can be further scaled up to Quad SPI, which is a high bandwidth low pin count interface which simultaneously uses 4 wire SPI to enable faster data transactions. Soft Error is a data error caused by background radiation. A lot of times that can be corrected by an error correcting code (ECC), which is data that is encoded with an extra parity bit which can detect and even correct those errors. Finally, Failures in Time (FIT) per Megabit of Data is just the projected failure rate of the device. One FIT per Megabit is equivalent to one failure per billion device hours.