A key differentiator between FPGA families is how they handle I/O. Cyclone® III devices offer key I/O enhancements to improve flexibility for easier I/O placements, reduce board space, increase system performance, and improve signal integrity. First, all 8 banks can interface to any I/O standard or external memory. Certain banks are still optimized for highest performance for memory interfaces and LVDS communication. For example, the top and bottom banks are optimized for memory interface performance, while the left and right banks are optimized for LVDS performance. 2 additional registers in the I/O cell increase DDR interface performance by improving the Write margin.