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This slide summarizes the key external memory interfaces supported by the Cyclone® III device family as well as maximum performance specifications for each interface. A combination of hardware modifications and IP design combine to improve external memory interface performance, improve flexibility, and vastly simplify design timing closure requirements. Cyclone® III memory interfaces can only be implemented using the new PHY architecture because the Cyclone® II static PHY implementation is not available for it.
PTM Published on: 2011-10-14
Thailand