Field-Programmable Gate Array (FPGA) Primer – Day 3
Simulation is a way to determine how well your Verilog design responds to external signals. Simulation can also be used as a debugging tool. Today’s lecture will describe how to enable a Vivado simulation module, or test-bench, and produce simulated signals to apply to our target Verilog design.
Part List
รูปภาพ | Manufacturer Part Number | คำอธิบาย | Available Quantity | ราคา | ดูรายละเอียด | |
---|---|---|---|---|---|---|
![]() | ![]() | 471-048 | BASYS 3 ARTIX-7 FPGA TRAINER BOA | 0 - Immediate | See Page for Pricing | ดูรายละเอียด |